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PCI2050 数据表(PDF) 21 Page - Texas Instruments

部件名 PCI2050
功能描述  PCI-TO-PCI BRIDGE
PDF  81 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

PCI2050 数据表(HTML) 21 Page - Texas Instruments

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2–9
Table 2–7. Secondary PCI System
TERMINAL
NAME
PDV
NO.
GHK
NO.
I/O
DESCRIPTION
S_CLKOUT9
S_CLKOUT8
S_CLKOUT7
S_CLKOUT6
S_CLKOUT5
S_CLKOUT4
S_CLKOUT3
S_CLKOUT2
S_CLKOUT1
S_CLKOUT0
42
41
39
38
36
35
33
32
30
29
N6
N3
N1
M5
M3
M2
L5
L6
L2
L1
O
Secondary PCI bus clocks. Provide timing for all transactions on the secondary PCI bus. Each
secondary bus device samples all secondary PCI signals at the rising edge of its corresponding
S_CLKOUT input.
S_CLK
21
J3
I
Secondary PCI bus clock input. This input syncronizes the PCI2050 to the secondary bus clocks.
S_CFN
23
J6
I
Secondary external arbiter enable. When this signal is high, the secondary external arbiter is enabled.
When the external arbiter is enabled, the PCI2050 S_REQ0 pin is reconfigured as a secondary bus
grant input to the bridge and S_GNT0 is reconfigured as a secondary bus master request to the
external arbiter on the secondary bus.
S_RST
22
J5
O
Secondary PCI reset. S_RST is a logical OR of P_RST and the state of the secondary bus reset bit
(bit 6) of the bridge control register (offset 3Eh, see Section 4.32). S_RST is asynchronous with
respect to the state of the secondary interface CLK signal.



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