TC54VC2802ECBSTP datasheet(3/3 Pages) TELCOM

3 / 3 page

4-281

TELCOM SEMICONDUCTOR, INC.

TC54

VOLTAGE DETECTOR

TIMING CHART

MARKING

VIN

DETECT VOLTAGE VDET

MINIMUM OPERATING

VOLTAGE

VHYST

VDET

OUTPUT VOLTAGE

RELEASE

VOLTAGE

RESET

VOLTAGE

GROUND LEVEL

–

= output (Nch or CMOS) plus first voltage digit

23 45 6

Nch

M N P R S

CMOS

C D E F H

ex: CMOS 3.x =

kkkk

= first voltage decimal (0-9)

ex: CMOS 3.4 =

kkkk

= assembly lot number

= 54_ (fixed)

= output (C = CMOS, N = Nch)

= first voltage digit (2-6)

= first voltage decimal (0-9)

= extra feature code : fixed : 0

= detecting accuracy

1 =

± 1.0% (custom), 2 = ± 2.0% (standard)

= assembly lot number

SOT-89-3

SOT-23A-3

TO-92

DESCRIPTION OF OPERATION

Refer to the Timing Chart below. In normal steady-state

operation, when VIN > V

–

DET, the output will be at a logic high.

In the case of the TC54V, this is an open-drain condition. If

and when the input falls below V

–

DET, the output will pull down

(Logic 0) to VSS. Generally, VOUT can pull down to within

0.5V of VSS at rated output current and input voltage. (See

the Electrical Characteristics section).

The output, VOUT, will stay valid until the input voltage

falls below the Minimum Operating Voltage, VIN(MIN), of

1.5V. Below this minimum operating voltage, the output is

undefined. During power-up or anytime VIN has fallen below

VIN (MIN), VOUT will remain undefined until VIN rises above

VIN(MIN), at which time the output will become valid. VOUT

will be in its active low state while VIN(MIN) < VIN < V+DET.

(V+DET = V

–

DET + VHYST). If and when the input rises above

DET, the output will assume its inactive state. (High for

TC54VC, open-drain for TC54VN).

APPLICATIONS

Refer to TelCom Semiconductor Application Note #2,

Using the TC54 Voltage Detector.

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