SN28835

1/2-INCH NTSC TIMER

SOCS023B – FEBRUARY 1991

12

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

VSS

INLVL

+V

244

243

12

Odd

244

244

243

2

1

12

or 1024

244 or 256

2

1

244

243

2

1

(driver output)

DPI

ABIN

GT

PI

PS

T

VD

Vertical-Dump

Frequency

(3.58 MHz

or 2 MHz)

Even

Odd

Even

GP

Figure 8. PI, PS, T, and ABIN Timing

NOTES: A. When the vertical-dump frequency is 2 MHz (chosen by a low level on VDS), the duty cycle of T, PS, and

PI is 4/7 high and 3/7 low; the duty cycle is 50% for a vertical-dump frequency of 3.58 MHz.

B. When GPS is high, VD is connected internally to GP.

C. Neither SC nor SC(90) is used for the 3.58-MHz clock.

D. GP goes low when VD is low. PI, PS, T, and GT begin clocking after VD goes high.

E. The 90

° phase shift between T, PS, and PI pulses is equal to one 14-MHz crystal-oscillator clock period.