PE55D Series 3.3 V

PECL Clock Oscillators

September 2007

www.pletronics.com

425-776-1880

6

3

4

1

2

6

5

Mechanical:

Inches

mm

A

0.197 +

_0.006

5.00 +

_0.15

B

0.125 +

_0.006

3.20 +

_0.15

C

0.053 max

1.35 max

D

1

0.050

1.27

E

1

0.050

1.27

F

1

0.004

0.10

G

1

0.039

1.00

H

1

0.025

0.63

Contacts

:

Gold 11.8 µinches

0.3 µm minimum over

Nickel 50 to 350 µinches

1.27 to 8.89 µm

Not to Scale

I

1

0.020

0.50

J

1

0.004R

0.10R

K

1

0.008R

0.20R

Pad

Function

Note

1

Output

Enable/Disable

When this pad is not connected the oscillator shall operate.

When this pad is <0.30 volts, the output will be inhibited (high impedance state.)

Recommend connecting this pad to V

2

No connect

There is no internal connection to this pad

3

Ground (GND)

4

Output

Both outputs must be terminated and biased for proper operation. The ideal

termination is 50 ohms connected to 2.0V below the Supply Voltage.

5

Output*

6

Supply Voltage

(V

Recommend connecting appropriate power supply bypass capacitors as close as

possible.

Layout and application information

Recommend connecting Pad 1 and Pad 2 together to permit the design to accept Enable/Disable input on

either pad

For Optimum Jitter Performance, Pletronics recommends:

•

a ground plane under the device

•

no large transient signals (both current and voltage) should be routed under the device

•

do not layout near a large magnetic field such as a high frequency switching power supply

•

do not place near piezoelectric buzzers or mechanical fans.