UM0470

Debug module (DM)

23/37

4.6

Timing description

This paragraph defines when the Debug Module stalls the CPU when using the different

breakpoint sources.

●

The STM8 instruction can be modelized in time with an op-code/operand FETCH

phase DECODE and EXECUTION phases as shown in Figure 12.

The timing information is based on this models.

Figure 12.

STM8 Instruction Model

4.7

Abort

The stall is generated immediately on writing the STALL bit in the DM_CSR2 register.

Figure 13.

STM8 Debug Module Stall Timing

4.8

Data breakpoint

A stall is generated when SWIM is active, after the end of the current instruction execution.

Figure 14.

STM8 DM Data Break Timing

OP-CODE/operand

DECODE

EXECUTE

FETCH

t

INSTRUCTION

1-5 bytes

t

INSTRUCTION 1

INSTRUCTION 2

INSTRUCTION 3

STALL REQUEST

DM Stall generated

t

DATA BREAK REQUEST

Stall generated

Dec2.n

D_rd1

Exe2.1

D_wr1

Fetch2

...Exe3(stalled)...