SN54F74, SN74F74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SDFS046A – MARCH 1987 – REVISED OCTOBER 1993

Copyright

2–1

POST OFFICE BOX 655303

Small-Outline Packages, Ceramic Chip

Carriers, and Standard Plastic and Ceramic

300-mil DIPs

description

These devices contain two independent positive-

edge-triggered D-type flip-flops. A low level at the

preset (PRE) or clear (CLR) inputs sets or resets

the outputs regardless of the levels of the other

inputs. When PRE and CLR are inactive (high),

data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the

positive-going edge of the clock pulse. Clock

triggering occurs at a voltage level and is not

directly related to the rise time of the clock pulse.

Following the hold-time interval, data at the

D input may be changed without affecting the

levels at the outputs.

The SN54F74 is characterized for operation over

the full military temperature range of – 55

°C to

125

°C. The SN74F74 is characterized for

operation from 0

°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

D

Q

Q

L

H

X

X

H

L

H

LX

XL

H

L

LX

X

H†

H†

H

H

↑

HH

L

H

H

↑

LL

H

H

H

L

X

Q0

Q0

† The output levels are not guaranteed to meet the

minimum levels for VOH. Furthermore, this

configuration is nonstable; that is, it will not persist

when PRE or CLR returns to its inactive (high)

level.

SN54F74 ...J PACKAGE

SN74F74 ...D OR N PACKAGE

(TOP VIEW)

SN54F74 . . . FK PACKAGE

(TOP VIEW)

32

1 20 19

910 11 12 13

4

5

6

7

8

18

17

16

15

14

2D

NC

2CLK

NC

2PRE

1CLK

NC

1PRE

NC

1Q

NC – No internal connection

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1CLR

1D

1CLK

1PRE

1Q

1Q

GND

2CLR

2D

2CLK

2PRE

2Q

2Q

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.