SN54HC03, SN74HC03

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

WITH OPEN-DRAIN OUTPUTS

SCLS077B – MARCH 1984 – REVISED MAY 1997

1

POST OFFICE BOX 655303

Small-Outline (D) and Ceramic Flat (W)

Packages, Ceramic Chip Carriers (FK), and

Standard Plastic (N) and Ceramic (J)

300-mil DIPs

description

These devices contain four independent 2-input

NAND gates. They perform the Boolean function

Y = A

• B or Y = A + B in positive logic. The

open-drain outputs require pullup resistors to

perform correctly. They may be connected to

other open-drain outputs to implement active-low

wired-OR or active-high wired-AND functions.

The SN54HC03 is characterized for operation

over the full military temperature range of –55

°C

to 125

°C. The SN74HC03 is characterized for

operation from –40

°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

Y

H

H

L

L

XH

X

L

H

1

1A

2

1B

1Y

3

4

2A

5

2B

2Y

6

9

3A

10

3B

3Y

8

12

4A

13

4B

4Y

11

&

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, N, and W packages.

logic diagram (positive logic)

A

B

Y

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2A

2B

2Y

GND

4B

4A

4Y

3B

3A

3Y

SN54HC03 . . . J OR W PACKAGE

SN74HC03 ...D OR N PACKAGE

(TOP VIEW)

32 1 20 19

910 11 1213

4

5

6

7

8

18

17

16

15

14

4A

NC

4Y

NC

3B

1Y

NC

2A

NC

2B

SN54HC03 . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

Copyright

© 1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.