©2008 CADEKA Microcircuits LLC

www.cadeka.com

13

PRELIMINARY Data Sheet

The quality of the input clock is extremely important for

high-speed, high-resolution ADCs. The contribution to SNR

from clock jitter with a full scale signal at a given frequency

is shown in equation 1.

jitter measured in seconds. The rms jitter is the total of all

jitter sources including the clock generation circuitry, clock

distribution and internal ADC circuitry.

For applications where jitter may limit the obtainable per-

formance, it is of utmost importance to limit the clock jitter.

This can be obtained by using precise and stable clock refer-

ences (e.g. crystal oscillators with good jitter specifications)

and make sure the clock distribution is well controlled. It

might be advantageous to use analog power and ground

planes to ensure low noise on the supplies to all circuitry

in the clock distribution. It is of utmost importance to avoid

crosstalk between the ADC output bits and the clock and

between the analog input signal and the clock since such

crosstalk often results in harmonic distortion.

The jitter performance is improved with reduced rise and

fall times of the input clock. Hence, optimum jitter per-

formance is obtained with LVDS or LVPECL clock with fast

edges. CMOS and sine wave clock inputs will result in

slightly degraded jitter performance.

If the clock is generated by other circuitry, it should be

retimed with a low jitter master clock as the last operation

before it is applied to the ADC clock input.

Digital Outputs

Digital output data are presented on parallel CMOS form.

outputs. The output drivers are dimensioned to drive

ommended to minimize the load to ensure as low tran-

sient switching currents and resulting noise as possible. In

applications with a large fanout or large capacitive loads,

it is recommended to add external buffers located close to

the ADC chip.

The timing is described in the Timing Diagram section.

Note that the load or equivalent delay on CLK_EXT always

should be lower than the load on data outputs to ensure

sufficient timing margins.

The digital outputs can be set in tristate mode by setting

the OE_N signal high.

The CDK2308 employs digital offset correction. This means

that the output code will be 4096 with the positive and

negative inputs shorted together(zero differential). How-

ever, small mismatches in parasitics at the input can cause

this to alter slightly. The offset correction also results in

possible loss of codes at the edges of the full scale range.

With “NO” offset correction, the ADC would clip in one

end before the other, in practice resulting in code loss at

the opposite end. With the output being centered digitally,

the output will clip, and the out of range flags will be set,

before max code is reached. When out of range flags are

set, the code is forced to all ones for over-range and all

zeros for under-range.

Data Format Selection

The output data are presented on offset binary form

format. Details are shown in Table 1 on page 14.

Reference Voltages

The reference voltages are internally generated and buff-

ered based on a bandgap voltage reference. No external

decoupling is necessary, and the reference voltages are

not available externally. This simplifies usage of the ADC

since two extremely sensitive pins, otherwise needed, are

removed from the interface.

Operational Modes

The operational modes are controlled with the PD_N and

SLP_N pins. If PD_N is set low, all other control pins are

overridden and the chip is set in Power Down mode. In this

mode all circuitry is completely turned off and the internal

clock is disabled. Hence, only leakage current contributes

to the Power Down Dissipation. The startup time from this

mode is longer than for other idle modes as all references

need to settle to their final values before normal operation

can resume.

The SLP_N bus can be used to power down each channel

independently, or to set the full chip in Sleep Mode. In this

mode internal clocking is disabled, but some low band-

width circuitry is kept on to allow for a short startup time.

However, Sleep Mode represents a significant reduction in

supply current, and it can be used to save power even for

short idle periods.

The input clock should be kept running in all idle modes.

However, even lower power dissipation is possible in Power

Down mode if the input clock is stopped. In this case it is

important to start the input clock prior to enabling active mode.