©2008 CADEKA Microcircuits LLC

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6

Data Sheet

Functional Description

Within the CDK3402/3403 are three identical 8-bit D/A

converters, each with a current source output. External

loads are required to convert the current to voltage out-

puts. Data inputs RGB7-0 are overridden by the BLANK

on-green video signals.

Digital Inputs

All digital inputs are TTL-compatible. Data is registered

on the rising edge of the CLK signal. Following one stage

rising edge of CLK.

Clock Input - CLK

The clock input is TTL-compatible and all pixel data is

registered on the rising edge of CLK. It is recommended

that CLK be driven by a dedicated TTL buffer to avoid

reflection induced jitter, overshoot, and undershoot.

Pixel Data Inputs - R7-0, B7-0, G7-0

TTL-compatible Red, Green and Blue Data Inputs are reg-

istered on the rising edge of CLK.

SYNC and BLANK

SYNC and BLANK inputs control the output level (Figure 2

and Table 1, on the previous page) of the D/A converters

during CRT retrace intervals. BLANK forces the D/A outputs

to the blanking level while SYNC = L turns off a current

source that is connected to the green D/A converter. SYNC

L sets the green output to 0.0V during the sync tip. SYNC

and BLANK are registered on the rising edge of CLK.

Data: 660mV max.

Pedestal: 54mV

Sync: 286mV

Figure 2. Normal Output Levels

BLANK gates the D/A inputs and sets the pedestal voltage.

If BLANK = HIGH, the D/A inputs are added to a pedestal

which offsets the current output. If BLANK = Low, data

inputs and the pedestal are disabled.

Sync Pulse Input - SYNC

source which forms a sync pulse on the Green D/A con-

verter output. SYNC is registered on the rising edge of

CLK with the same pipeline latency as BLANK and pixel

data. SYNC does not override any other data and should

be used only during the blanking interval.

Since this is a single-supply D/A and all signals are posi-

tive-going, sync is added to the bottom of the Green D/A

range. So turning SYNC OFF means turning the current

source ON. When a sync pulse is desired, the current

source is turned OFF. If the system does not require sync

pulses from the Green D/A converter, SYNC should con-

nected to GND.

Blanking Input - BLANK

When BLANK is LOW, pixel inputs are ignored and the

D/A converter outputs fall to the blanking level. BLANK

is registered on the rising edge of CLK and has the same

pipeline latency as SYNC.

D/A Outputs

Each D/A output is a current source. To obtain a voltage

output, a resistor must be connected to ground. Output

voltage depends upon this external resistor, the reference

voltage, and the value of the gain-setting resistor con-

Normally, a source termination resistor of 75Ω is connect-

ed between the D/A current output pin and GND near the

D/A converter. A 75Ω line may then be connected with an-

other 75Ω termination resistor at the far end of the cable.

This “double termination” presents the D/A converter with

a net resistive load of 37.5Ω.

The CDK3402/3403 may also be operated with a single

75Ω terminating resistor. To lower the output voltage

swing to the desired range, the nominal value of the

The R, G, and B current source outputs of the D/A

converters are capable of driving RS-343A/SMPTE-170M

compatible levels into doubly-terminated 75Ω lines. Sync

pulses may be added to the Green D/A output.