©2004-2009 CADEKA Microcircuits LLC

www.cadeka.com

11

Data Sheet

Figure 4: Overdrive Recovery

Driving Capacitive Loads

The

the response of the CLC2005. A small series resistance

in the

achieve maximum bandwidth with less than 1dB of peak-

Figure 5: Typical Topology for driving a capacitive load

Layout Considerations

General layout and supply bypassing play major roles

in high frequency performance. Cadeka has evaluation

boards to use as a guide for high frequency layout and to

aid in device testing and characterization. Follow the steps

below as a basis for high frequency layout:

n

Include 6.8μF and 0.1μF ceramic capacitors

n

Place the 6.8μF capacitor within 0.75 inches of the

power pin

n

Place the 0.1μF capacitor within 0.1 inches of the

power pin

n

Remove the ground plane under and around the part,

especially near the input and output pins to reduce

parasitic capacitance

n

Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts shown in Figure 7

for more information.

When evaluating only one channel, complete the following

on the unused channel:

1. Ground the non-inverting input.

2. Short the output to the inverting input.

Evaluation Board Information

The following evaluation boards are available to aid in the

testing and layout of this device:

Eval Board

Description

Products

CEB006

Dual Channel, Dual Supply

8 lead SOIC

CLC2005SO8

Evaluation board schematics and layouts are shown in

Figure 6 and Figure 7.

The CEB006 evaluation board is built for dual supply

operation. Follow these steps to use the board in a single

supply application:

not directly connected to the ground plane.

Figure 6: Evaluation Board Schematic

Time (20ns/div)

Output

Input

G = 5

+

-