IMP690ACSLASHD datasheet(5/10 Pages) A1PROS

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IMP690A

IMP690A , 692A

, 692A , 802L, 802M, 805L

, 802L, 802M, 805L

Application Information

Reset Output

It is important to initialize a microprocessor to a known state in

response to specific events that could create code execution errors

and “lock-up”. The reset output of these supervisory circuits send

a reset pulse to the microprocessor in response to power-up,

power-down/power-loss or a watchdog time-out. The reset pulse

width, tRS, is typically around 200ms and is LOW for the

IMP690A, IMP692A, IMP802 and HIGH for the IMP805L.

Power-up reset occurs when a rising VCC reaches the reset thresh-

old, VRT, forcing a reset condition in which the reset output is

asserted in the appropriate logic state for the duration of tRS.

Figure 2 shows the reset pin timing.

Power-loss or “brown-out” reset occurs when VCC dips below the

reset threshold resulting in a reset assertion for the duration of tRS.

The reset signal remains asserted as long as VCC is between VRT

and 1.1V, the lowest VCC for which these devices can provide a

guaranteed logic-low output. To ensure logic inputs connected to

the IMP690A/692A/802 RESET pin are in a known state when

VCC is under 1.1V, a 100kΩ pull-down resistor at RESET is needed:

the logic-high IMP805L will need a pull-up resistor to VCC.

A Watchdog time-out reset occurs when a logic “1” or logic “0” is

continuously applied to the WDI pin for more than 1.6 seconds.

After the duration of the reset interval, the watchdog timer starts

a new 1.6 second timing interval; the microprocessor must service

the watchdog input by changing states or by floating the WDI pin

before this interval is finished. If the WDI pin is held either HIGH

or LOW, a reset pulse will be triggered every 1.8 seconds (the 1.6

second timing interval plus the reset pulse width tRS).

Microprocessor Interface.

The IMP690 has logic-LOW RESET output while the IMP805 has

an inverted logic-HIGH RESET output. Microprocessors with bi-

directional reset pins (69HC11 for example) can pose a problem

when the supervisory circuit and the microprocessor output pins

attempt to go to opposite logic states. The problem can be

resolved by placing a 4.7k

Ω resistor between the RESET output

and the microprocessor reset pin. This is shown in Figure 3. Since

the series resistor limits drive capabilities, the reset signal to other

devices should be buffered.

VCC

VOUT

PFI

WDI

GND

VBATT

PFO

IMP690A, IMP692A, IMP802L, IMP802M,

IMP805L

RESET

(RESET)

( ) IMP805L

Battery-Switchover

Circuit

Reset

Generator

Watchdog

Timer

3.5V

1.25V

0.8V

690A_03.eps

Figure 1. Block Diagram

VCC

VOUT

VBATT = PFI = 3.0V

IOUT = 0mA

PFO

+ 5V

+ 0V

3.0V

+ 5V

+ 0V

+ 5V

+ 0V

+ 5V

+ 0V

( ) IMP805L

3.0V

RESET

(RESET)

690A_04.eps

tRS

Figure 2. Timing Diagram

690A_05.eps

GND

RESET

VCC

IMP690A

VCC

4.7k

Buffered RESET to Other System Components

Figure 3. Interfacing with bi-directional microprocessor

reset inputs

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