IMP802LEPA datasheet(3/10 Pages) A1PROS

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IMP690A

IMP690A , 692A

, 692A , 802L, 802M, 805L

, 802L, 802M, 805L

Absolute Maximum Ratings

Pin Description

Pin Terminal Voltage with Respect to Ground

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 6.0V

VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 6.0V

All Other Inputs* . . . . . . . . . . . . . . . . . . . –0.3V to (VCC + 0.3V)

Input Current at VCC . . . . . . . . . . . . . . . . . . 200mA

Input Current at VBATT . . . . . . . . . . . . . . . . . 50mA

Input Current at GND . . . . . . . . . . . . . . . . . 20mA

Output Current:

VOUT . . . . . . . . . . . . . . . Short circuit protected

All Other Inputs . . . . . . . . . . . . . . . . . . . 20mA

Rate of Rise: VBATT and VCC . . . . . . . . . . 100V/µs

Continuous Power Dissipation

Plastic DIP (derate 9mW/

°C above 70°C) . . . 800mW

SO (derate 5.9mW/

°C above 70°C) . . . . . . . . 500mW

CerDIP (derate 8mW/

°C above 70°C) . . . . . . 650mW

Operating Temperature Range (C Devices) . . . . 0

°C to 70°C

Operating Temperature Range (E Devices) . . . . –40

°C to 85°C

Storage Temperature Range . . . . . . . . . . . . . . . . . –65

°C to 160°C

Lead Temperature Soldering, (10 sec) . . . . . . . . 300

°C

* The input voltage limits on PFI and WDI may be exceeded if the

current is limited to less than 10mA

These are stress ratings only and functional operation is not implied.

Exposure to absolute maximum ratings for prolonged time periods may

affect device reliability.

Pin Number

IMP690A/IMP692A

IMP802L/IMP802M

IMP805L

Name

Function

VOUT

Voltage supply for RAM. When VCC is above the reset threshold, VOUT

connects to VCC through a P-channel MOS device. If VCC falls below the

reset threshold, this output will be connected to the backup supply at

VBATT (or VCC, whichever is higher) through the MOS switch to provide

continuous power to the CMOS RAM.

VCC

+5V power supply input

GND

Ground

PFI

Power failure monitor input. PFI is connected to the internal power fail

comparator which is referenced to 1.25V. The power fail output (PFO)

is active LOW but remains HIGH if PFI is above 1.25V. If this feature is

unused, the PFI pin should be connected to GND or VOUT.



PFO

Power-fail output.



PFO is active LOW whenever the PFI pin is less than

1.25V.

WDI

Watchdog input. The WDI input monitors microprocessor activity. An

internal timer is reset with each transition of the WDI input. If WDI is held

HIGH or LOW for longer than the watchdog timeout period, typically 1.6

seconds, RESET (or



RESET) is asserted for the reset pulse width time,

tRS, of 140ms, minimum.

––––



RESET

Active-LOW reset output. When triggered by VCC falling below the reset

threshold or by watchdog timer timeout, RESET (or



RESET) pulses low

for the reset pulse width, tRS, typically 200ms. It will remain low if VCC is

below the reset threshold (4.65V in the IMP690A/IMP802L and 4.4V in

the IMP692A/IMP802L) and remains low for 200ms after VCC rise above

the reset threshold.

––––

RESET

Active-HIGH reset output. The inverse of



RESET.

VBATT

Auxiliary power or backup-battery input. VBATT should be connected to

GND if the function is not used. This input has about 40mV of hysteresis

to prevent rapid toggling between VCC and VBATT.

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