RESET/RESET Operation

The RESET/RESET signals are designed to start or return a

µP/µC to a known state.

asserted. During a power-up sequence, the reset outputs remain

asserted until the supply rises above the threshold level. The

resets are deasserted approximately 200ms after crossing the

threshold.

the reset outputs are asserted. If a brownout occurs during an

already initiated reset period, the reset period will extend for an

additional reset period of 200ms.

The IMP708 devices have dual reset outputs, one active LOW and

one active HIGH. The IMP706P has a single active HIGH reset and

the IMP706/R/S/T/J devices have an active LOW reset output.

IMP Part RESET Polarity Threshold Watchdog Timer

IMP706P

HIGH

2.63V

Yes

IMP706R

LOW

2.63V

Yes

IMP706S

LOW

2.93V

Yes

IMP706T

LOW

3.08V

Yes

IMP706J

LOW

4.00V

Yes

IMP708R

Both: HIGH & LOW

2.63V

No

IMP708S

Both: HIGH & LOW

2.93V

No

IMP708T

Both: HIGH & LOW

3.08V

No

IMP708J

Both: HIGH & LOW

4.00V

No

Manual Reset (MR)

The active-LOW manual reset input is pulled high by an internal

20k

Ω pull-up resistor and can be driven low by CMOS/TTL logic

or a mechanical switch to ground. An external debounce circuit is

unnecessary since the 140ms minimum reset time will debounce

mechanical pushbutton switches. The minimum MR input pulse

IMP706P/R/S/T/J, IMP708R/S/T/J

IMP706P/R/S/T/J, IMP708R/S/T/J

6

408-432-9100/www.impweb.com

©

1999 IMP, Inc.

5V

0V

5V

0V

5V

0V

5V

0V

v

RT

WDO

RESET

MR

t

MD

t

RS

t

RS

t

MR

MR externally

set low

706P_05.eps

Watchdog Timing

WDI Three-state operation

5V

0V

5V

t

WD

t

WP

t

WD

t

WD

0V

5V

0V

RESET triggered by MR

WDI

WDO

RESET

706P_04.eps

width is 0.5

By connecting the watchdog output (WDO) and MR, a watchdog

timeout forces a RESET to be generated.

Watchdog Timer

A watchdog timer available on the IMP706P/R/S/T/J monitors

µP/µC activity. If activity is not detected within 1.6 seconds on the

Watchdog Input (WDI), the internal timer puts the Watchdog

Output (WDO) into a LOW state. WDO will remain LOW until

activity is detected at WDI.

The watchdog function is disabled, meaning it is cleared and not

counting, if WDI is floated or connected to a three-stated circuit.

The watchdog timer is also disabled if RESET is asserted. When

RESET becomes inactive and the WDI input sees a high or low

watchdog timer will begin a 1.6 second countdown. Additional

transitions at WDI will reset the watchdog timer and initiate a

new countdown sequence.

WDO will also become LOW and remain so, whenever the supply

pulse width for WDO as there is for the RESET outputs. If WDI is float-

ed, WDO essentially acts as a low supply voltage output indicator.

Power-failure detection with auxiliary comparator

All devices have an auxiliary comparator with 1.25V trip point.

The output, PFO, is active LOW and the noninverting input is PFI.

This comparator can be used as a supply voltage monitor with an

external resistor voltage divider. As the monitored voltage level

falls, PFI is reduced causing the PFO output to go LOW.

Normally PFO interrupts the processor so the system can be shut

down in a controlled manner.

Detail Descriptions