SN74ALVC10

TRIPLE 3-INPUT POSITIVE-NAND GATE

SCES106D – JULY 1997 – REVISED OCTOBER 1998

2

POST OFFICE BOX 655303

logic diagram, each gate (positive logic)

Y

A

B

C

–0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

127

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package

182

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package

170

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 4)

MIN

MAX

UNIT

VCC

Supply voltage

1.65

3.6

V

VCC = 1.65 V to 1.95 V

0.65

× VCC

VIH

High-level input voltage

VCC = 2.3 V to 2.7 V

1.7

V

VCC = 2.7 V to 3.6 V

2

VCC = 1.65 V to 1.95 V

0.35

× VCC

VIL

Low-level input voltage

VCC = 2.3 V to 2.7 V

0.7

V

VCC = 2.7 V to 3.6 V

0.8

VI

Input voltage

0

VCC

V

VO

Output voltage

0

VCC

V

VCC = 1.65 V

–4

IOH

High level output current

VCC = 2.3 V

–12

mA

IOH

High-level output current

VCC = 2.7 V

–12

mA

VCC = 3 V

–24

VCC = 1.65 V

4

IOL

Low level output current

VCC = 2.3 V

12

mA

IOL

Low-level output current

VCC = 2.7 V

12

mA

VCC = 3 V

24

∆t/∆v

Input transition rise or fall rate

0

5

ns/V

TA

Operating free-air temperature

–40

85

°C

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.