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FEATURES

D, DGV, NS, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1OE

1A

1Y

2OE

2A

2Y

GND

4OE

4A

4Y

3OE

3A

3Y

DESCRIPTION/ORDERING INFORMATION

1

1OE

2

1A

1Y

3

4

2OE

5

2A

2Y

6

10

3OE

9

3A

3Y

8

13

4OE

12

4A

4Y

11

SN74ALVC125

QUADRUPLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES110H – JULY 1997 – REVISED SEPTEMBER 2004

•

Operates from 1.65 V to 3.6 V

•

•

±24-mA Output Drive at 3.3 V

•

Latch-up Performance Exceeds 250 mA Per

JESD 17

•

ESD Performance Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

The SN74ALVC125 features independent line drivers with 3-state outputs. Each output is disabled when the

associated output-enable (OE) input is high.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

ORDERABLE PART NUMBER

TOP-SIDE MARKING

Tube

SN74ALVC125D

SOIC - D

ALVC125

Tape and reel

SN74ALVC125DR

SOP - NS

Tape and reel

SN74ALVC125NSR

ALVC125

-40

°C to 85°C

Tube

SN74ALVC125PW

TSSOP - PW

VA125

Tape and reel

SN74ALVC125PWR

TVSOP - DGV

Tape and reel

SN74ALVC125DGVR

VA125

(1)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

Y

OE

A

L

H

H

L

L

L

H

X

Z

LOGIC DIAGRAM (POSITIVE LOGIC)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 1997–2004, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.