LTC2228 datasheet(21/28 Pages) LINER

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LTC2228/LTC2227/LTC2226

222876fb

APPLICATIONS INFORMATION

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2228/LTC2227/

LTC2226 is 65Msps (LTC2228), 40Msps (LTC2227), and

25Msps (LTC2226). For the ADC to operate properly, the

CLK signal should have a 50% (±5%) duty cycle. Each

half cycle must have at least 7.3ns (LTC2228), 11.8ns

(LTC2227), and 18.9ns (LTC2226) for the ADC internal cir-

cuitry to have enough settling time for proper operation.

An optional clock duty cycle stabilizer circuit can be used

if the input clock has a non 50% duty cycle. This circuit

uses the rising edge of the CLK pin to sample the analog

input. The falling edge of CLK is ignored and the internal

falling edge is generated by a phase-locked loop. The input

clock duty cycle can vary from 40% to 60% and the clock

duty cycle stabilizer will maintain a constant 50% internal

duty cycle. If the clock is turned off for a long period of

time, the duty cycle stabilizer circuit will require a hundred

clock cycles for the PLL to lock onto the input clock. To

use the clock duty cycle stabilizer, the MODE pin should be

connected to 1/3VDD or 2/3VDD using external resistors.

The lower limit of the LTC2228/LTC2227/LTC2226 sample

rate is determined by droop of the sample-and-hold circuits.

The pipelined architecture of this ADC relies on storing

analog signals on small-valued capacitors. Junction leak-

age will discharge the capacitors. The speciﬁed minimum

operating frequency for the LTC2228/LTC2227/LTC2226

is 1Msps.

LTC2228/27/26

222876 F14

OVDD

VDD

0.1μF

43Ω

TYPICAL

DATA

OUTPUT

OGND

OVDD

0.5V

TO 3.6V

PREDRIVER

LOGIC

DATA

FROM

LATCH

Figure 14. Digital Output Buffer

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input

voltage, the digital data bits and the overﬂow bit.

Table 1. Output Codes vs Input Voltage

AIN+ – AIN–

(2V RANGE)

D11-D0

(OFFSET BINARY)

D11-D0

(2’s COMPLEMENT)

>+1.000000V

+0.999512V

+0.999024V

1111 1111 1111

1111 1111 1110

0111 1111 1111

0111 1111 1110

+0.000488V

0.000000V

–0.000488V

–0.000976V

1000 0000 0001

1000 0000 0000

0111 1111 1111

0111 1111 1110

0000 0000 0001

0000 0000 0000

1111 1111 1111

1111 1111 1110

–0.999512V

–1.000000V

<–1.000000V

0000 0000 0001

0000 0000 0000

1000 0000 0001

1000 0000 0000

Digital Output Buffers

Figure 14 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OVDD and OGND, isolated

from the ADC power and ground. The additional

N-channel transistor in the output driver allows operation

down to low voltages. The internal resistor in series with

the output makes the output appear as 50Ω to external

circuitry and may eliminate the need for external damping

resistors.

As with all high speed/high resolution converters, the

digital output loading can affect the performance. The

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