www.ti.com

A

Y

2

4

A

Y

1

3

SN74LVC1G04

SINGLE INVERTER GATE

SCES214S – APRIL 1999 – REVISED OCTOBER 2005

ORDERING INFORMATION

ORDERABLE PART NUMBER

NanoStar™ – WCSP (DSBGA)

SN74LVC1G04YEAR

0.17-mm Small Bump – YEA

NanoFree™ – WCSP (DSBGA)

0.17-mm Small Bump – YZA

SN74LVC1G04YZAR

(Pb-free)

_ _ _CC_

NanoStar™ – WCSP (DSBGA)

SN74LVC1G04YEPR

0.23-mm Large Bump – YEP

Reel of 3000

NanoFree™ – WCSP (DSBGA)

0.23-mm Large Bump – YZP

SN74LVC1G04YZPR

(Pb-free)

–40

°C to 85°C

NanoStar™ – WCSP (DSBGA)

0.23-mm Large Bump – YZV

SN74LVC1G04YZVR

PREVIEW

(Pb-free)

Reel of 3000

SN74LVC1G04DBVR

SOT (SOT-23) – DBV

C04_

Reel of 250

SN74LVC1G04DBVT

Reel of 3000

SN74LVC1G04DCKR

SOT (SC-70) – DCK

Reel of 250

SN74LVC1G04DCKT

CC_

SOT (SOT-553) – DRL

Reel of 4000

SN74LVC1G04DRLR

(1)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2)

DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.

YEA/YZA, YEP/YZP/YZV: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and

one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,

• = Pb-free).

FUNCTION TABLE

INPUT

OUTPUT

A

Y

H

L

L

H

LOGIC DIAGRAM (POSITIVE LOGIC)

(DBV, DCK, DRL, YEA, YEP, YZA, AND YZP PACKAGE)

LOGIC DIAGRAM (POSITIVE LOGIC)

(YZV PACKAGE)

2