AM26LS32

SEMICONDUCTOR

TECHNICAL DATA

QUAD EIA–422/3 LINE

RECEIVER WITH

THREE–STATE OUTPUTS

ORDERING INFORMATION

PIN CONNECTIONS

Order this document by AM26LS32/D

PC SUFFIX

PLASTIC PACKAGE

CASE 648

D SUFFIX

PLASTIC PACKAGE

CASE 751B

(SO–16)

Device

Operating

Temperature Range

Package

AM26LS32PC

MC26LS32D*

TA = 0 to 70°C

Plastic DIP

SO–16

9

–

+

–

8

7

6

5

4

3

2

1

10

11

12

13

14

+

–

+

–

Inputs A

+

VCC

16

3–State

Control

GND

Output B

Output D

15

3–State

Control

Inputs C

Inputs B

Inputs D

Outputs A

Output C

1

MOTOROLA ANALOG IC DEVICE DATA

QUAD EIA-422/423 Line

Receiver with Three-State

Outputs

Motorola

′s Quad EIA–422/3 Receiver features four independent receiver

chains which comply with EIA Standards for the Electrical Characteristics of

Balanced/Unbalanced Voltage Digital Interface Circuits. Receiver outputs

are 74LS compatible, three–state structures which are forced to a high

impedance state when Pin 4 is a Logic “0” and Pin 12 is a Logic “1.” A PNP

device buffers each output control pin to assure minimum loading for either

Logic “1” or Logic “0” inputs. In addition, each receiver chain has internal

hysteresis circuitry to improve noise margin and discourage output instability

for slowly changing input waveforms. A summary of AM26LS32 features

include:

(PIA Compatible)

Are Open, Terminated or Shorted

* Note that the surface mount MC26LS32D device uses the same die as in the plastic DIP

Representative Block Diagram

Hysteresis

Amplifier

Amplifier

Three–State

Control

Inputs

Output

Differential

Inputs

Input

Network

Level

Translator

Level

Translator

© Motorola, Inc. 1995