THMC50

REMOTE/LOCAL TEMPERATURE MONITOR AND

FAN CONTROLLER WITH SMBus INTERFACE

SLIS090 – JULY 1999

21

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

diode fault status

The THMC50 provides for indications of a fault (open or short-circuited) with the remote thermal diode. Before

a remote thermal diode conversion is updated, the status of the remote thermal diode is checked for an

open-circuited or short-circuited condition. If such a fault condition occurs, a status bit is set in the status register,

and an interrupt is generated (unless masked). An open or shorted condition on the remote diode causes the

remote temperature value to read 0x80, does not have an effect on the FAN_SPD output, and does not cause

a THERM condition.

The following table describes the THMC50 behavior under various remote diode fault conditions:

FAULT CONDITION ON

Remote_Diode+ and Remote_Diode_

REMOTE TEMPERATURE

(REGISTER 0x26)

THERM

ACTIVATED

INT

GENERATED

REMOTE DIODE DEFAULT

STATUS BITS SET

Any remote diode pin open

0x80

No†

Yes‡

Yes

Short between Remote_Diode

± pins

0x80

No†

Yes‡

Yes

Remote_Diode+ short to supply

0x80

No†

Yes‡

Yes

Remote_Diode+ short to GND

0x80

No†

Yes‡

Yes

Remote_Diode– shorted to supply

0x80

No†

Yes‡

Yes

Remote_Diode– shorted to GND

Normal operation

No§

No§

No

† THERM will not be asserted due to this fault, however, THERM could still activate due to a valid internal temperature THERM condition or if

THERM is asserted externally.

‡ INT will not be generated if the Remote diode fault is masked. A remote temperature error INT or a remote temperature error status bit will not

be generated by a faulted remote diode.

§ THERM or INT will be asserted if the temperature in 0x26 meets the criteria for a THERM or INT event and INT is not masked.

interrupt output

All interrupts are indicated in the interrupt status register and its mirror register. The INT output has an individual

mask register and individual masks for each interrupt. This hardware interrupt line can also be enabled/disabled

in the configuration register. When enabled, the INT line reflects all interrupt error conditions. INT can be

generated from the following sources:

on either the local or remote thermal diode.

on the remote thermal diode inputs.

general-purpose input - GPI

The GPI logic input terminal allows the THMC50 SMBus host to read the logic state of this input terminal by

reading bit 4 of the interrupt status register (0x41). The logic state of the GPI terminal reported in bit 4 of the

interrupt status register (0x41) is inverted from the actual GPI logic state if bit 6 of the configuration register

(0x40) is set to a 1. If bit 6 of the configuration register (0x40) is set to a 0, then bit 4 of the interrupt status register

(0x41) reports the same logic state present on the GPI terminal. The GPI interrupt bit can be masked by setting

bit 4 of the interrupt mask register (0x43) to 1. Note that the state of GPI is not latched into bit 4; this bit simply

reflects the state or inverted state of the GPI terminal. If this bit is 1, reading this register does not clear it to 0.

interrupt clearing

Reading the interrupt status register or the interrupt status register mirror outputs the contents of the register

and resets that register only. A subsequent read done before the next conversion is complete indicates a cleared

register. Allow at least 1.5 seconds for all registers to be updated between reads. In summary, the interrupt

status register clears upon being read, and requires at least 1.5 seconds to be updated. When the interrupt

status register clears, the INT output also clears until the registers are updated by the next conversion.