THMC40SOPD datasheet(11/17 Pages) TI

11 / 17 page

THMC40, THMC41

VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS

SLIS097 – MARCH 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PWM duty cycle control voltage (VPWM) – digital PWM control input (continued)

Figure 8 illustrates the relationship between VOUT output duty-cycle and a 0–3.3-V digital PWM input control

signal.

3.3-V Duty Cycle Input to RC Filter

2030

405060

100

RUN STATE

SLEEP

STATE

VOUT % =((3.3 V ×

(Input%

÷100)-0.5)÷1.8) × 100

VSLEEP=21%

VSTART = 24%

Must be exceeded to

enter run state

Figure 8. Relationship of VOUT Duty Cycle, VSLEEP, VSTART vs 0–3.3 V PWM Input Duty Cycle

sleep/run state

Sleep-state and run-state modes are provided, as illustrated in Figures 6 and 8. The sleep state is intended to

minimize VPWR (fan) supply current requirements (300 µA typical) when cooling fan operation is not required.

This feature is especially beneficial for PC OEMs needing to meet the

instantly available PC requirements

without the use of additional external circuitry.

The sleep state is engaged when the VPWM input voltage is below the VSLEEP threshold (0.7 V typical, 11.1%

duty cycle). During the sleep state, all output drivers are turned off and any unused circuits are powered down

to minimize current drain. Once sleep state is engaged, VPWM must exceed the VSTART threshold (0.8 V typical,

17% duty cycle) to disable the sleep state and enter the run state, allowing the motor to be driven. Once the

run state is engaged, outputs VOUT, PHA, and PHB are active and the VPWM voltage can be decreased to obtain

minimum fan speed down to the VSLEEP threshold. This procedure allows the user to overcome initial motor

stiction with a PWM duty cycle of 17% to avoid the possibility of false locked rotor detection during initial start-up.

See Figure 6 for the VPWM input voltage relationship to sleep mode and VOUT duty cycle.

A control device with a voltage range of 0 V to 2.5 V is recommended to provide the adjustable VPWM reference

voltage to the THMC40 and THMC41. A 2.5-V DAC is an optimal choice as the controlling circuitry, whether as

a stand-alone device, or as an integrated function in a multiple-function device. Using a control device without

a minimum 0.5-V to 2.3-V range reduces the RPM control range of the fan motor and may not allow duty-cycle

settings of 0% and/or 100%.

thermal shutdown

The THMC40 and THMC41 provide protection against excessive device temperature with a thermal sensor that

monitors the die temperature. Should some operating or abnormal condition cause the die temperature to

exceed TTSD, the thermal shutdown threshold (165°C typical), all output drivers are turned off. Once TTSD has

been exceeded, the die temperature must fall below a hysteresis temperature (typical TTSD –15°C) before the

output drivers are re-enabled.

THMC40SOPD 数据表(PDF) 11 Page - Texas Instruments

THMC40SOPD 数据表(HTML) 11 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

数据表下载