THS0842

DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER

WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

10

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

COUT

01

234

567

9

10

11

8

12

131415

I5

DA(7–0)

CLK

Q

I

th

tsu

td(pipe-I)

N

N

N+1

N+1

N+2

N+2

N+3

N+3

N+4

N+4

td(A)

tJ(A)

16

DAB(15–0)

I4

I3

I2

I1

I–1

I–2

I–3

I–4

Q4

DB(7–0)

Q3

Q2

Q1

Q–1

Q–2

Q–3

Q–4

Q5

td(0)

DAB(15–0) is the combination of both DA and DB. It illustrates when both buses have valid data for latching.

I3 & Q3

I4 & Q4

I5 & Q5

I2 & Q2

I1 & Q1

td(pipe-Q)

td(0)

COUT

NOTE A: The relationship between CLK and COUT/COUT is not fixed and depends on the power-on conditions. Data out should be referenced

to COUT and COUT.

Figure 2. Timing Diagram, Dual Bus Output