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THS4601CDDA 数据表(PDF) 13 Page - Texas Instruments |
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THS4601CDDA 数据表(HTML) 13 Page - Texas Instruments |
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13 / 27 page ![]() THS4601 SLOS388B – OCTOBER 2001 – REVISED JUNE 2002 13 www.ti.com APPLICATION INFORMATION designing the transimpedance circuit (continued) As indicated, the current source typically sets the requirements for gain, speed, and dynamic range of the amplifier. For a given amplifier and source combination, achievable performance is dictated by the following parameters: the amplifier’s gain-bandwidth product, the amplifier’s input capacitance, the source capacitance, the transimpedance gain, the amplifier’s slew rate, and the amplifier’s output swing. From this information, the optimal performance of a transimpedance circuit using a given amplifier can be determined. Optimal is defined here as providing the required transimpedance gain with a maximally flat frequency response. For the circuit shown in Figure 26, all but one of the design parameters is known; the feedback capacitor must be determined. Proper selection of the feedback capacitor prevents an unstable design, controls pulse response characteristics, provides maximally flat transimpedance bandwidth, and limits broadband integrated noise. The maximally flat frequency response results with CF calculated as shown in equation 1, where CF is the feedback capacitor, RF is the feedback resistor, CS is the total source capacitance (including amplifier input capacitance and parasitic capacitance at the inverting node), and GBP is the gain-bandwidth product of the amplifier in hertz. C F + 1 pR F GBP ) 1 pR F GBP 2 ) 4C S pR F GBP 2 Once the optimal feedback capacitor has been selected, the transimpedance bandwidth can be calculated with equation 2. F –3dB + GBP 2 pR F CS ) C F _ + CIDIFF CICM CP RF CF CD IDIODE NOTE: The total source capacitance is the sum of several distinct capacitances. Cs = CICM + CIDIFF + CP + CD Where: CICM is the common-mode input capacitance. CIDIFF is the differential input capacitance. CD is the diode capacitance. CP is parasitic capacitance at the inverting node. Figure 27. Transimpedance Analysis Circuit (1) (2) |
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