TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM

HIGH-PERFORMANCE IMPACT

™ PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992

POST OFFICE BOX 655303

13

power-up reset

Following power up, all registers are reset to zero. The output level depends on the polarity selected during

programming. This feature provides extra flexibility to the system designer and is especially valuable in

monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and

feedback setup times are met.

1.5 V

tsu ‡

tpd †

tw

VOL

VOH

VIL

VIH

5 V

VCC

Active High

Registered Output

Active Low

Registered Output

CLK

4 V

VOH

VOL

1.5 V

1.5 V

(600 ns typ, 1000 ns MAX)

State Unknown

1.5 V

State Unknown

† This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.

‡ This is the setup time for input or feedback.

Figure 3. Power-Up Reset Waveforms

programming information

Texas Instruments programmable logic devices can be programmed using widely available software and

inexpensive device programmers.

Complete programming specifications, algorithms, and the latest information on hardware, software, and

firmware are available upon request. Information on programmers capable of programming Texas Instruments

programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI

distributor, or by calling Texas Instruments at (214) 997-5666.