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TLC551CD 数据表(PDF) 10 Page - Texas Instruments |
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TLC551CD 数据表(HTML) 10 Page - Texas Instruments |
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10 / 16 page ![]() TLC551, TLC551Y LinCMOS ™ TIMERS SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION 0.1 µF 0.1 µF CT CL RL Output RB RA GND TRIG THRES RESET DISCH CONT VDD OUT VDD 2/3 VDD 1/3 VDD GND tPHL tPLH tc(H) tc(L) CIRCUIT TRIGGER AND THRESHOLD VOLTAGE WAVEFORM TLC551 3 8 5 4 7 6 2 1 VDD Figure 3. Astable Operation Connecting TRIG to THRES, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor CT charges through RA and RB to the threshold voltage level (approximately 0.67 VDD) and then discharges through RB only to the value of the trigger voltage level (approximately 0.33 VDD). The output is high during the charging cycle (tc(H)) and low during the discharge cycle (tc(L)). The duty cycle is controlled by the values of RA, and RB, and CT, as shown in the equations below. t c(H) [ C T (R A ) R B )In2 (In 2 + 0.693) t c(L) [ C T R B In 2 Period + t c(H) ) t c(L) [ C T (R A ) 2R B )In2 Output driver duty cycle + t c(L) t c(H) ) t c(L) [ 1– R B R A ) 2R B Output waveform duty cycle + t c(H) t c(H) ) t c(L) [ R B R A ) 2R B The 0.1- µF capacitor at CONT in Figure 3 decreases the period by about 10%. The formulas shown above do not allow for any propagation delay times from TRIG and THRES to DISCH. These delay times add directly to the period and create differences between calculated and actual values that increase with frequency. In addition, the internal on-state resistance ron during discharge adds to RB to provide another source of timing error in the calculation when RB is very low or ron is very high. |
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