TLC548C, TLC548I, TLC549C, TLC549I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996

4

POST OFFICE BOX 655303

recommended operating conditions

TLC548

TLC549

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

UNIT

Supply voltage, VCC

3

5

6

3

5

6

V

Positive reference voltage, Vref+ (see Note 3)

2.5

VCC VCC+0.1

2.5

VCC VCC+0.1

V

Negative reference voltage, Vref – (see Note 3)

– 0.1

0

2.5

–0.1

0

2.5

V

Differential reference voltage, Vref+, Vref – (see Note 3)

1

VCC VCC+0.2

1

VCC VCC+0.2

V

Analog input voltage (see Note 3)

0

VCC

0

VCC

V

High-level control input voltage, VIH (for VCC = 4.75 V to 5.5 V)

2

2

V

Low-level control input voltage, VIL (for VCC = 4.75 V to 5.5 V)

0.8

0.8

V

Input/output clock frequency, fclock(I/O) (for VCC = 4.75 V to 5.5 V)

0

2.048

0

1.1

MHz

Input/output clock high, twH(I/O) (for VCC = 4.75 V to 5.5 V)

200

404

ns

Input/output clock low, twL(I/O) (for VCC = 4.75 V to 5.5 V)

200

404

ns

Input/output clock transition time, tt(I/O)

(for VCC = 4.75 V to 5.5 V) (see Note 4 and Operating Sequence)

100

100

ns

Duration of CS input high state during conversion, twH(CS)

(for VCC = 4.75 V to 5.5 V) (see Operating Sequence)

17

17

µs

Setup time, CS low before first I/O CLOCK, tsu(CS)

(for VCC = 4.75 V to 5.5 V) (see Note 5)

1.4

1.4

µs

TLC548C, TLC549C

0

70

0

70

°C

TLC548I, TLC549I

–40

85

–40

85

°C

NOTES:

3. Analog input voltages greater than that applied to REF+ convert to all ones (11111111), while input voltages less than that applied

to REF– convert to all zeros (00000000). For proper operation, the positive reference voltage Vref+, must be at least 1 V greater than

the negative reference voltage, Vref–. In addition, unadjusted errors may increase as the differential reference voltage, Vref+ – Vref– ,

falls below 4.75 V.

4. This is the time required for the I/O CLOCK input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity

of normal room temperature, the devices function with input clock transition time as slow as 2

µs for remote data acquisition

applications in which the sensor and the ADC are placed several feet away from the controlling microprocessor.

5. To minimize errors caused by noise at the CS input, the internal circuitry waits for two rising edges and one falling edge of internal

system clock after CS

↓ before responding to control input signals. This CS setup time is given by the ten and tsu(CS) specifications.