TLC5904

LED DRIVER

SLLS391 – NOVEMBER 1999

13

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

shift register latch for gray scale data

The shift register latch for the gray scale data is set as an 8

× 1 byte configuration at the 8 bit mode, and as a

16

× 1 byte configuration at the 16 bit mode. The gray scale data, configured as 8 bits, represents the time when

constant current output is being turned on, and the data range is 0 to 255 (00h to FFh). When the gray scale

data is 0, the time is shortest, and the output is not turned on(light off). On the other hand, when the gray scale

data is 255, the time is longest, and it turns on during the time of the 255 clocks from GSCLK. The configuration

of the shift register and latch for gray scale data is shown below.

(8 bits)

OUT15

Data

XLATCH

(8 bits)

OUT14

Data

(8 bits)

OUT1

Data

(8 bits)

OUT0

Data

Latch for Gray Scale Data

16th byte

DIN7 MSB

DIN0 LSB

DOUT0 to 7

Shift Register for Gray Scale Data

15th byte

DIN7 MSB

DIN0 LSB

2nd byte

DIN7 MSB

DIN0 LSB

1st byte

DIN7 MSB

DIN0 LSB

DIN0 to 7

DCLK

16 Bit Mode (MODE=H, RSEL0 and RSEL1=L)

(8 bits)

OUT15, 14

Data

XLATCH

(8 bits)

OUT13, 12

Data

(8 bits)

OUT3, 2

Data

(8 bits)

OUT1, 0

Data

Latch for Gray Scale Data

8th byte

DIN7 MSB

DIN0 LSB

DOUT0 to 7

Shift Register for Gray Scale Data

7th byte

DIN7 MSB

DIN0 LSB

2nd byte

DIN7 MSB

DIN0 LSB

1st byte

DIN7 MSB

DIN0 LSB

DIN0 to 7

DCLK

8 Bit Mode (MODE=L, RSEL0 and RSEL1=L)

Figure 3. Relationship Between Shift Register and Latch for Gray Scale Data