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TLV5633 INTERFACED to an Intel MCS

P2 A(15-8)

P0 AD(7-0)

ALE

WR

D(7-0)

A

B

C

G1

G2A

G2B

A(1-0)

D(7-0)

CS

WE

REF

A(15-0)

AD(7-0)

CS(7-0)

8

8

8

16

8

8

74AC373

8xC51

74AC138

TLV5633

A15

A2

A3

A4

2

Q(7-0)

Y(7-0)

G2A

SPD

PWR

LDAC

LE

OE

OUT

To Other Devices Requiring

Voltage Reference

P3.5

TLV5633C

TLV5633I

SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006

bus and the data bus of the controller are multiplexed on port 0 (non page mode) to save port pins. To separate

the address bits and the data bits, the controller provides a dedicated signal, address latch enable (ALE), which

is connected to a latch at port 0.

An address decoder is required to generate the chip select signal for the TLV5633. In this example, a simple

3-to-8 decoder (74AC138) is used for the interface as shown in Figure 15. The DAC is memory mapped at

addresses 0x8000/1/2/3 within the data memory address space and mirrored every 32 address locations

(0x8020/1/2/3, 0x8040/1/2/3, etc.). In a typical microcontroller system, programmable logic should be used to

generate the chip select signals for the entire system.

The data pins and the WE pin of the TLV5633 can be connected directly to the multiplexed address and data

bus and the WR signal of the controller.

The application uses the TLV5633 device's internal reference at 2.048 V. The LDAC pin is connected to P3.5

and is used to update the DAC after both data bytes have been written.

14

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