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TMS320VC5410 数据表(PDF) 46 Page - Texas Instruments

部件名 TMS320VC5410
功能描述  FIXED-POINT DIGITAL SIGNAL PROCESSOR
PDF  79 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TMS320VC5410 数据表(HTML) 46 Page - Texas Instruments

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TMS320VC5410
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
46
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
memory and parallel I/O interface timing (continued)
memory write
switching characteristics over recommended operating conditions (MSTRB = 0) [H = 0.5 tc(CO)]†
(see Figure 19)
PARAMETER
’VC5410-100
’VC5410-120
UNIT
PARAMETER
MIN
MAX
MIN
MAX
UNIT
td(CLKL-A)
Delay time, CLKOUT low to address valid
– 1
4
– 1
6
ns
tsu(A)MSL
Setup time, address valid before MSTRB low
2H – 5
2H – 5
ns
td(CLKL-D)W
Delay time, CLKOUT low to data valid
0
5
0
7
ns
tsu(D)MSH
Setup time, data valid before MSTRB high
2H – 5
2H + 5
2H – 5
ns
th(D)MSH
Hold time, data valid after MSTRB high
2H – 5
2H + 5
2H – 5
ns
td(CLKL-MSL)
Delay time, CLKOUT low to MSTRB low
– 1
4
– 1
6
ns
tw(SL)MS
Pulse duration, MSTRB low
2H – 5
2H – 5
ns
td(CLKL-MSH)
Delay time, CLKOUT low to MSTRB high
– 1
4
– 1
6
ns
† Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
td(CLKL-MSH)
td(CLKL-A)
CLKOUT
A[22:0]
D[15:0]
MSTRB
R/W
PS/DS
tsu(A)MSL
td(CLKL-D)W
tsu(D)MSH
th(D)MSH
tw(SL)MS
td(CLKL-MSL)
Figure 19. Memory Write (MSTRB = 0)
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.



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