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TNETE2201APJD 数据表(PDF) 8 Page - Texas Instruments

部件名 TNETE2201APJD
功能描述  1.25-GIGABIT ETHERNET TRANSCEIVER
PDF  19 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TNETE2201APJD 数据表(HTML) 8 Page - Texas Instruments

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TNETE2201A
1.25-GIGABIT ETHERNET TRANSCEIVER
SLLS342 – MARCH 1999
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
comma character not on expected boundary
When synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then
word realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character
following the misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown
in Figure 2. The 10b specification requires that RCLK cycles can not be truncated and can only be stretched
or stalled in their current state during realignment. With this design the maximum stretch that occurs is an extra
10 bit times. This occurs during a worst case scenario when the K28.5 is aligned to the falling edge of RBC1
instead of the rising edge. This system transmits a minimum of three consecutively ordered K28.5 data sets
between frames and ensures that the receiver sees at least two of K28.5 sets (the fabric is allowed to drop one).
Figure 2 shows the timing characteristics of the data realignment.
Systems that do not require framed data can disable byte alignment by tying SYNCEN low.
When a synchronization character is detected the SYNC signal is asserted high and is aligned with the K28.5
character. The duration of the SYNC-signal pulse is equal to the duration of the data which is half an RCLK
period.
RBC0
RBC1
SYNC
Serial Rx Data Stream
DIN_RxP – DIN_RxN
K28.5
Dxx.x
Dxx.x
Dxx.x
K28.5
Dxx.x
RD0 – RD9
K28.5
Dxx.x
Dxx.x
Dxx.x
Dxx.x
K28.5
20 Bit Times
(MAX)
Typical Receive
Path Latency = 18 ns
Dxx.x
Dxx.x
Dxx.x
Worst Case
Misaligned K28.5
Corrupted Data
Misalignment
Corrected
10 Bit Times
10 Bit Times
Dxx.x
K28.5
K28.5
Dxx.x
K28.5
Figure 2. Word Realignment Timing Characteristics Waveforms
data reception latency
The serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the
aligned parallel word with RD0 received as first bit. The receive latency is typically 18 ns.



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