TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

13

POST OFFICE BOX 655303

RECEIVER SECTION

differential electrical characteristics over recommended operating conditions (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

|VID |

Differential input voltage (peak-to-peak)

See Figure 5

400

2600

mV

receiver and phase-locked loop performance characteristics over recommended operating

conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT†

Jitter tolerance

See P802.3Z specification

74.9%

UI

From power up at 2 nF capacitor value

500

µs

Data acquisition lock time

From power up at 0.1

µF capacitor value

(See Note 4)

10

ms

Data relock time

From synchronization loss

2500

ns

† UI is the unit interval of a single bit (800 ps).

NOTE 4: A filter capacitor value of 0.1

µF can be used with the following consideration: The tracking bandwidth of the PLL will be reduced due

to the larger filter capacitor. This reduces the transmit and receive PLL’s ability to reject low-frequency noise or wonder in the voltage

supply or datastream. Care must be taken in the filtering of the supply VCC_TX (terminal 18) and VCC_RX (terminal 50) to reject power

supply noise.

receive clock timing requirements over recommended operating conditions (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fclk

Clock frequency, RBC0

62.5

MHz

fclk

Clock frequency, RBC1 (180 deg out of phase with RBC0)

62.5

MHz

tr4

Data rise time

See Figure 6

0.7

4

ns

tf4

Data fall time

See Figure 6

0.7

4

ns

tr5

Rise time, single-ended output signal on RBC0 or RBC1

See Figure 6

0.7

2

ns

tf5

Fall time, single-ended output signal on RBC0 or RBC1

See Figure 6

0.7

2

ns

Duty cycle, RBC0 or RBC1

40%

60%

t(skew)

Skew time, RBC1

↑ to RBC0 ↑

See Figure 7

7.5

8

8.5

ns

tsu2

Setup time, RD0 – RD9, SYNC valid to RBC0

↑

See Figure 7

2.5

ns

tsu3

Setup time, RD0 – RD9, SYNC valid to RBC1

↑

See Figure 7

2.5

ns

tsu4

Setup time, RBC1

↑ to RD0 – RD9, SYNC invalid

See Figure 7

1.5

ns

tsu5

Setup time, RBC1

↑ to RD0 – RD9, SYNC invalid

See Figure 7

1.5

ns

Serial-to-parallel data latency

18

ns

† t(drift) is the minimum time for RBC0 or RBC1 to drift from 63.5 MHz to 64.5 MHz or from 60 MHz to 59 MHz from the RCLK lock value. This is

applicable under all input signal conditions with PLL locked to the REFCLK of DATA signals.

|VID |

0 V

|VID |

Figure 5. Differential Input Voltage (Peak-to-Peak) Timing Waveform