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TMS320C52PZ 数据表(PDF) 13 Page - Texas Instruments |
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TMS320C52PZ 数据表(HTML) 13 Page - Texas Instruments |
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13 / 91 page  TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 13 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Functions for the TMS320C52, TMS320LC52 in the PJ Package SIGNAL TYPE DESCRIPTION PARALLEL INTERFACE BUS A0 – A15 I/O/Z 16-bit external address bus (MSB: A15, LSB: A0) D0 – D15 I/O/Z 16-bit external data bus (MSB: D15, LSB: D0) PS, DS, IS O/Z Program, data, and I /O space select outputs, respectively STRB I/O/Z Timing strobe for external cycles and external DMA R/W I/O/Z Read / write select for external cycles and external DMA RD, WE O/Z Read and write strobes, respectively, for external cycles READY I External bus ready/ wait-state control input BR I/O/Z Bus request. Arbitrates global memory and external DMA SYSTEM INTERFACE / CONTROL SIGNALS RS I Reset. Initializes device and sets PC to zero MP/ MC I Microprocessor/microcomputer mode select. Enables internal ROM HOLD I Puts parallel I/ F bus in high-impedance state after current cycle HOLDA O/Z Hold acknowledge. Indicates external bus in hold state XF O/Z External flag output. Set /cleared through software BIO I I /O branch input. Implements conditional branches TOUT O/Z Timer output signal. Indicates output of internal timer INT1 – INT4 I External interrupt inputs NMI I Nonmaskable external interrupt SERIAL PORT INTERFACE DR I Serial receive-data input DX O/Z Serial transmit-data output. In high-impedance state when not transmitting CLKR I Serial receive-data clock input CLKX I/O/Z Serial transmit-data clock. Internal or external source FSR I Serial receive-frame-synchronization input FSX I/O/Z Serial transmit-frame-synchronization signal. Internal or external source EMULATION/JTAG INTERFACE TDI I JTAG-test-port scan data input TDO O/Z JTAG-test-port scan data output TMS I JTAG-test-port mode select input TCK I JTAG-port clock input TRST I JTAG-port reset (with pulldown resistor). Disables JTAG when low EMU0 I/O/Z Emulation control 0. Reserved for emulation use EMU1 / OFF I/O/Z Emulation control 1. Puts outputs in high-impedance state when low LEGEND: I = Input O = Output Z = High impedance |
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