May 2007

ASM3P623S00B/C/J/E/F/K

rev 0.4

Timing-Safe™ Peak EMI Reduction IC

7 of 18

Notice: The information in this document is subject to change without notice.

Switching Characteristics for ASM3P623S00B/C/J/E/F/K

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

Output Frequency

30pF load

20

50

MHz

Duty Cycle

Measured at VDD/2

40

50

60

%

Output Rise Time

6,7

Measured between 0.8V and 2.0V

2.5

nS

Output Fall Time

6,7

Measured between 2.0V and 0.8V

2.5

nS

Output-to-output skew

6

All outputs equally loaded

250

pS

Delay, CLKIN Rising Edge to

CLKOUT Rising Edge

6

Measured at VDD /2

±350

pS

Device-to-Device Skew

6

Measured at VDD/2 on the CLKOUT pins

of the device

700

pS

Cycle-to-cycle jitter

6

Loaded outputs

200

pS

PLL Lock Time

6

Stable power supply, valid clock presented

on CLKIN pin

1.0

mS

Notes:

5. CLKIN input has a threshold voltage of VDD/2

6. Parameter is guaranteed by design and characterization. Not 100% tested in production

7. The parameters are specified with loaded outputs.