November 2006

ASM3P2775A

rev 0.3

Notice: The information in this document is subject to change without notice.

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200 Campbell, CA 95008

• Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

Low Power Peak EMI Reducing Solution

Features

•

Generates an EMI optimized clock signal at the

output.

•

Integrated loop filter components.

•

Operates with a 3.3V Supply.

•

Operating current less than 4mA.

•

Low power CMOS design.

•

Input frequency range: 13MHz to 30MHz

•

Generates a 1X low EMI spread spectrum clock

of the input frequency.

•

Frequency deviation: ±1.75% (Typ) @14.7MHz

Input Frequency.

•

Available in 6-pin TSOT-23, 8-pin SOIC and 8-

pin TSSOP packages.

Product Description

The ASM3P2775A is a versatile spread spectrum

frequency modulator designed specifically for a wide

range of clock frequencies. The ASM3P2775A reduces

electromagnetic interference (EMI) at the clock source,

allowing system wide reduction of EMI of

all clock

dependent signals. The ASM3P2775A allows significant

system cost savings by reducing the number of circuit

board layers, ferrite beads and shielding that are

traditionally required to pass EMI regulations.

The ASM3P2775A uses the most efficient and optimized

modulation profile approved by the FCC and is

implemented by using a proprietary all digital method.

The ASM3P2775A modulates the output of a single PLL

in order to “spread” the bandwidth of a synthesized clock,

and more importantly, decreases the peak amplitudes of

its harmonics. This results in significantly lower system

EMI compared to the typical narrow band signal produced

by oscillators and most frequency generators. Lowering

EMI by increasing a signal’s bandwidth is called ‘spread

spectrum clock generation’.

Applications

The ASM3P2775A is targeted towards all portable

devices with very low power requirements like MP3

players and digital still cameras.

Key Specifications

Description

Specification

Supply voltages

VDD = 3.3V ± 0.3V

Cycle-to-Cycle Jitter

200pS (Max)

Output Duty Cycle

45/55% (worst case)

Modulation Rate Equation

Frequency Deviation

±1.75% (Typ) @ 14.7MHz

Block Diagram

ModOUT

VSS

XIN/CLKIN

Frequency

Divider

Feedback

Divider

Modulation

Phase

Detector

Loop

Filter

VCO

Output

Divider

PLL

VDD

PD

Crystal

Oscillator

XOUT