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ASM1832F 数据表(PDF) 6 Page - PulseCore Semiconductor |
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ASM1832F 数据表(HTML) 6 Page - PulseCore Semiconductor |
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6 / 9 page ![]() 6 of 9 Notice: The information in this document is subject to change without notice 3.3V µP Power Supply Monitor and Reset Circuit rev 1.6 October 2006 ASM1832 Notes 1. RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down until VCC falls below 2.0V. Watchdog Timeout Period tTD TD = VCC 500 1200 2000 ms Watchdog Timeout Period tTD TD Floating 250 610 1000 ms Output Voltage VOH I=-500µA, VCC < 2.7.V Note 1 VCC - 0.3V VCC - 0.1V V Output Current IOH Output = 2.4V, VCC >=2.7V 350 µA Output Current IOL Output = 0.4V, VCC >=2.7V 10 mA Input Leakage IIL -1.0 1.0 µA RESET Low Level VOL Note 1 0.4 V Internal Pull-up Resistor PBRST pin 40 k Ω Operating Current ICC1 Outputs open, VCC <= 3.6V and all inputs at VCC or GND 20 µA Input Capacitance CIN 5pF Output Capacitance COUT 7pF PBRST Manual Reset Minimum Low Time tPB PBRST = VIL 20 ms Reset Active Time tRST 250 610 1000 ms ST Pulse Width tST Must not exceed tRD mini- mum. Watchdog cannot be disabled. 20 ns VCC Fail Detect to RESET or RESET tRPD Pulses < 2 µs at VCCTP min- imum will not cause reset 58 µs VCC Slew Rate tF 20 µs PBRST Stable LOW to RESET and RESET Active tPDLY 20 ms VCC Detect to RESET or RESET inactive tRPU trise=5µs 250 610 1000 ms VCC Slew Rate tR 0ns Parameter Symbol Conditions Min Typ Max Unit |
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