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TPS5102 数据表(PDF) 21 Page - Texas Instruments |
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TPS5102 数据表(HTML) 21 Page - Texas Instruments |
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21 / 31 page ![]() TPS5102 DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER SLVS239 - SEPTEMBER 1999 21 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION synchronization (continued) Ct Rt TPS5102 An external resistor is added into the circuit, but Rt is still removed. Ct is kept to be a part of RC circuit generating triangle waveform for the controller. Assuming the peak value of the square is known, the resistor and the capacitor can be adjusted to achieve the correct peak-to-peak value and the offset value. layout guidelines Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise pickup and generation and can cause a good design to perform with less than expected results. With a range of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult than most general PCB designs. The general design should proceed from the switching node to the output, then back to the driver section and, finally, parallel the low-level components. Below are several specific points to consider before the layout of a TPS5102 design begins. D All sensitive analog components should be referenced to ANAGND. These include components connected to Vref5, Vref, INV, LH, and COMP. D Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect to the ground side of the bulk storage capacitors on VO, and drive ground will connect to the main ground plane close to the source of the low-side FET. D Connections from the drivers to the gate of the power FETs should be as short and wide as possible to reduce stray inductance. This becomes more critical if external gate resistors are not being used. D The bypass capacitor for VCC should be placed close to the TPS5102. D When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should be as short and as wide as possible. D When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from LH to LL) should be placed close to the TPS5102. D When configuring the high-side driver as a ground-referenced driver, LL should be connected to DRVGND. D The bulk storage capacitors across VIn should be placed close to the power FETS. High-frequency bypass capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the high-side FET and to the source of the low-side FET. D High-frequency bypass capacitors should be placed across the bulk storage capacitors on VO. D LH and LL should be connected very close to the drain and source, respectively, of the high-side FET. LH and LL should be routed very close to each other to minimize differential-mode noise coupling to these traces. D The output voltage sensing trace should be isolated by either ground trace or Vcc trace. |
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