FUNCTION TABLE

DEVICE INFORMATION

PACKAGE

SSC_SEL 0

1

8

VDD

SSC_SEL 1

2

7

OUT

GND

3

6

SSC_ON

IN

4

5

CDCS501

SSC_SEL 2

PACKAGE THERMAL RESISTANCE FOR TSSOP (PW) PACKAGE

(1)

CDCS501

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

SSC_ON

SSC_SEL 0

SSC_SEL 1

SSC_SEL 2

SPREAD AMOUNT

1

x

x

X

0.00%

0

0

0

0

1.00%

0

0

0

1

1.50%

0

0

1

0

1.00%

0

0

1

1

1.50%

0

1

0

0

0.50%

0

1

0

1

0.75%

0

1

1

0

0.00%

0

1

1

1

0.50%

PIN FUNCTIONS

PIN

NAME

NO.

Type

Description

IN

1

I

LVCMOS Clock Input

OUT

6

O

LVCMOS Clock Output

SSC_SEL 0, 1, 2

2, 3, 7

I

Spread Selection Pins, internal Pull-up

SSC_ON

5

I

SSC on/off Pin, active low; internal Pull-down

VDD

8

Power

3.3V Power Supply

GND

4

Ground

Ground

THERMAL AIRFLOW (CFM)

CDCS501PW 8-PIN TSSOP

UNIT

0

150

250

500

High K

149

142

138

132

°C / W

Low K

230

185

170

150

High K

65

°C / W

Low K

69

(1)

The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

2

Submit Documentation Feedback

Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s): CDCS501