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SSL3250A 数据表(PDF) 13 Page - NXP Semiconductors |
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SSL3250A 数据表(HTML) 13 Page - NXP Semiconductors |
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13 / 26 page ![]() SSL3250A_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 30 June 2009 13 of 26 NXP Semiconductors SSL3250A Photo flash dual LED driver The four protection circuits and their bits in the status register are as follows: • Overvoltage protection • Time-out protection • Overtemperature protection • Output short protection When a protection is triggered, switching of the IC is inhibited without a soft ramp-down of the current in the main LED and also the indicator LED will be switched off. To recover from this fault condition in I2C mode, write 00h to the current control register (00h) to clear the status register release the INT line. After clearing the status register, the current control register can be reloaded and the flash can be retriggered. Reloading the other registers is not necessary as they will not lose their value when an interrupt is generated. In Direct enable mode the status register is cleared and the INT line is released, by making both the EN1 and EN2 pins lO. 8.4.1 Overvoltage protection If the output voltage (VO) exceeds its limit (Vovp, see Table 9), switching of the converter is inhibited. The output voltage will exceed Vovp limit when no LEDs are connected between pins VO and LED. In some cases an overvoltage protection may occur when the LED pin is shorted to GND during the period a Flash is generated. The converter is trying to compensate for the loss of feedback current by increasing VO. When an overvoltage is encountered, the OVPtrig flag (bit 0) is set in the status register. 8.4.2 Untimed Flash mode To avoid overloading of the main LED during a flash in Direct enable mode or I2C control mode in untimed Flash mode (bit 4, TO_DEF = 0 in Timer control register 01h). A time-out timer limits the maximum ON time of the flash. In both control modes the flash time-out time is set to a fixed level of 820 ms. When the flash strobe signal is set to LOW in I2C control mode, bit 0 in register 02h is set to 0. When the EN1 signal is set to LOW before the time-out timer has expired in Direct enable mode, the time-out timer is reset. When a time-out situation is encountered, the TOtrig flag (bit 1) is set in the status register. See also Section 8.3.5. 8.4.3 Overtemperature protection If the chip temperature exceeds its limit (Totp, see Table 9), switching of the converter is inhibited until the temperature drops below its limit minus a small hysteresis. When an overtemperature situation is encountered, the OTtrig flag (bit 2) is set in the status register. |
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