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TDF8599B 数据表(PDF) 10 Page - NXP Semiconductors

部件名 TDF8599B
功能描述  I2C-bus controlled dual channel 43 W/4 W, single channel 85 W/1 W class-D power amplifier with load diagnostics
PDF  54 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

TDF8599B 数据表(HTML) 10 Page - NXP Semiconductors

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TDF8599B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
10 of 54
NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
8.3.4 Phase lock operation (Slave mode)
In Slave mode, Phase-Locked Loop (PLL) operation can be used to reduce the jitter effect
of the external oscillator signal connected to pin OSCIO. Phase lock operation is also
needed to enable phase staggering, see Section 8.4.2 on page 13. Phase lock operation
is enabled when the oscillator is in Slave mode by connecting two capacitors (CPLL_s and
CPLL_p) and a resistor (RPLL) between pin SSM and pin AGND (see Figure 8). Connecting
pin SSM to pin AGND disables phase lock operation and causes the slave to directly use
the external oscillator signal. Values for CPLL_s, CPLL_p and RPLL depend on the desired
loop bandwidth (BPLL) of the PLL. RPLL is given by: RPLL = 8.4 × BPLL Ω. The
corresponding values for CPLL_s and CPLL_p are given by Equation 3 and Equation 4:
(3)
Remark: CPLL_p is only needed when 1⁄4 π phase shift is selected. See Section 8.4.2 for
more detailed information.
(4)
When pin OSCIO is connected to a clock-master with Spread spectrum mode enabled,
the PLL loop bandwidth BPLL should be 100 × fSSM.
Table 7 lists all oscillator modes.
(1) Only needed when 1
⁄
4 π phase shift is
selected.
a. Off
b. On
Fig 8.
Phase lock operation
Table 7.
Oscillator modes
OSCSET pin
OSCIO pin
SSM pin
Oscillator modes
Rosc > 26 kΩ
output
CSSM to pin AGND
master, spread spectrum
Rosc > 26 kΩ
output
shorted to pin AGND
master, no spread spectrum
Rosc =0 Ω
input
CPLL + RPLL to pin AGND
slave, PLL enabled
Rosc =0 Ω
input
shorted to pin AGND
slave, PLL disabled
C
PLL_p
0.032
R
PLL
B
PLL
×
------------------------------- F
[]
=
C
PLL_s
0.8
R
PLL
B
PLL
×
------------------------------- F
[]
=
001aai776
100
µA
SSM
OSCSET
PLL
001aai777
100
µA
PLL
OSCSET
RPLL
CPLL_p(1)
CPLL_s
SSM



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