LT3582 datasheet(13/28 Pages) LINER

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LT3582/LT3582-5/LT3582-12

3582512f

CMDR: The Command Register is used to control various

functions of the chip. During shutdown and power-up the

CMDR is initialized to 00h.

The RSEL (Register Select) bits are functional only for

the LT3582. The LT3582-5 and LT3582-12 function as if

the RSEL bits are always “0”. These bits perform three

functions:

• Each RSEL bit instructs the chip whether to use the

conﬁguration data from the corresponding OTP byte

(RSELx=0) or the REG byte (RSELx=1). Changing an

RSELx bit immediately updates the chip conﬁguration.

• Each RSEL bit determines if I2C reads return data from

the corresponding OTP byte (RSELx=0) or the REG byte

(RSELx=1).

• OTP programming only programs data to the bytes with

corresponding RSEL bits set high.

Setting the SWOFF bit immediately disables the Boost and

Inverting power switches and opens the output disconnect

PMOS switch. It is recommended to set this bit before

writing new conﬁguration data. This can prevent unex-

pected chip behavior while modifying the conﬁguration

and also forces a soft-start after SWOFF is cleared (see

Soft-Start and Power-up Sequencing). Writing “1” to the

RST bit resets the internal I2C logic and the CMDR register.

Reading bit 6 of the CMDR returns the FAULT bit indicating

if an OTP programming attempt may have failed. FAULT

is cleared during reset, power-up, or by writing a “1” to

the CF (Clear Fault) bit. Conditions that set the FAULT bit

are (1) OTP programming in which the VPP voltage is too

low or (2) attempted OTP programming when the LOCK

bit is set.

OTP write attempts that set the FAULT bit due

to low VPP voltage should be considered failures and the

device should be discarded. Attempts to re-program the

OTP memory after the FAULT bit has been set are not

recommended. Finally, setting the WOTP bit starts the

OTP programming.

Table 1: LT3582 Series Register Map

REGIS-

TER

ADDRESS

REGIS-

TER

NAME

BIT

NAME

DESCRIPTION

00h

REG0/

OTP0

7:0

VOUTPOutputVoltage(00h=3.2V,

BFh = 12.75V)

01h

REG1/

OTP1

7:0

VOUTNOutputVoltage(00h=1.2V,

FFh = 13.95V)

Reserved, Write to 0

LOCK

Lockout Bit: See “OTP Program-

ming Lockout” Section.

02h

REG2/

OTP2

5VPLUS VOUTP Output Voltage Bit: In-

crease VOUTP by ~25mV

4:3

IRMP

RAMPP & RAMPN Pullup Cur-

rent: IRAMP = (2) IRMP μA

PDDIS Power-Down Discharge Enable.

PUSEQ Must be 11 if Set.

1:0

PUSEQ Power-Up Sequencing: 00 =

Outputs Disabled, 01 = VOUTN

Ramp 1st, 10 = VOUTP Ramp 1st,

11 = Both Ramp Together

WOTP Write OTP Memory

6CF/

FAULT

Clear Fault/OTP Programming

Fault

5RST

Reset

4SWOFF Switches-Off

04h

CMDR

Reserved, Write to 0

2RSEL2 Register Select 2 (0=OTP2,

1=REG2)

1RSEL1 Register Select 1 (0=OTP1,

1=REG1)

0RSEL0 Register Select 0 (0=OTP0,

1=REG0)

OTP0/REG0 & OTP1/REG1: Data in addresses 00h &

01h is used to set the output voltages of the Boost and

Inverting converters respectively. See Setting the Output

Voltages for more information.

APPLICATIONS INFORMATION

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