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UCC2913 数据表(PDF) 6 Page - Texas Instruments |
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UCC2913 数据表(HTML) 6 Page - Texas Instruments |
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6 / 9 page ![]() 6 UCC1913 UCC2913 UCC3913 1 µAR V PL FET • Therefore, the maximum average power dissipation in the MOSFET can be approximated by: P VIMAX AR V IMAX A R FET avg FET PL FET PL () = •• • =• • 1 1 µ µ Notice that in the approximation, VFET cancels. therefore, average power dissipation is limited in the NMOS pass element. Overload Comparator The linear amplifier in the UCC1913 ensures that the output NMOS does not pass more than IMAX (which is VIMAX/RS). In the event the output current exceeds the programmed IMAX by 0.2V/RS, which can only occur if the output FET is not responding to a command from the IC, the CT pin will begin charging with I3, 1mA, and con- tinue to charge to approximately 8V. This allows a con- stant fault to show up on the SD/FLT pin, and also since the voltage on CT will only charge past 2.5V in an over- load fault mode, it can be used for detection of output FET failure or to build in redundancy in the system. Determining External Component Values Referring now to Figure 3. To set RVDD the following must be achieved: () () V R V RR mA IN VDD min > + + 10 12 2 In order to estimate the minimum timing capacitor, CT, several things must be taken into account. For example, given the schematic below as a possible (and at this point, a standard) application, certain external compo- nent values must be known in order to estimate CT(min). Now, given the values of COUT, Load, RSENSE, VSS, and the resistors determining the voltage on the IMAX pin, the user can calculate the approximate startup time of the node VOUT. This startup time must be faster than the time it takes for CT to charge to 2.5V (relative to VSS), and is the basis for estimating the minimum value of CT. In order to determine the value of the sense resistor, RSENSE, assuming the user has determined the fault cur- rent, RSENSE can be calculated by: R mV I SENSE FAULT = 50 APPLICATION INFORMATION (cont.) Figure 3. ∞ Figure 4. Plot average power vs. FET voltage for increasing values of RPL. SHUTDOWN SD/FLT 7 R4 R3 VSS LEVEL SHIFT LOCAL VDD LOCAL GND FAULT OUT Figure 5. Possible level shift circuitry to interface to the UCC1913. |
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