LTM8025

8

8025f

PIN FUNCTIONS

capacitor and the output load between these pins and

GND pins.

GND (Bank 2): Tie these GND pins to a local ground plane

below the LTM8025 and the circuit components. In most

applications, the bulk of the heat flow out of the LTM8025

is through these pads, so the printed circuit design has

a large impact on the thermal performance of the part.

See the PCB Layout and Thermal Considerations sections

this net.

internal regulator and to the internal power switch. This

pin must be locally bypassed with an external, low ESR

capacitor; see Table 1 for recommended values.

AUX (Pin G5): Low Current Voltage Source for BIAS. In

adjacent to the BIAS pin to ease printed circuit board rout-

is not intended to deliver a high current, so do not draw

current from this pin to the load. If this pin is not tied to

BIAS, leave it floating.

BIAS (Pin H5): The BIAS pin connects to the internal power

bus. Connect to a power source greater than 2.8V and less

than 25V. If the output is greater than 2.8V, connect this

pin there. If the output voltage is less, connect this to a

voltage source between 2.8V and 25V. Also, make sure

RUN/SS (Pin L5): Pull the RUN/SS pin below 0.2V to

shut down the LTM8025. Tie to 2.5V or more for normal

operation. If the shutdown feature is not used, tie this pin

see the Applications Information section.

SYNC (Pin L6): This is the external clock synchronization

input. Ground this pin for low ripple Burst Mode operation

at low output loads. Tie to a stable voltage source greater

than 0.7V to disable Burst Mode operation. Do not leave

this pin floating. Tie to a clock source for synchroniza-

tion. Clock edges should have rise and fall times faster

than 1μs. See the Synchronization section in Applications

Information.

RT (Pin G7): The RT pin is used to program the switching

frequency of the LTM8025 by connecting a resistor from

this pin to ground. Table 2 gives the resistor values that

correspond to the resultant switching frequency. Minimize

the capacitance at this pin.

SHARE (Pin H7): Tie this to the SHARE pin of another

LTM8025 when paralleling the outputs. Otherwise, do

not connect.

PGOOD (Pin J7): The PGOOD pin is the open-collector

output of an internal comparator. PGOOD remains low

until the ADJ pin is within 10% of the final regulation

and RUN/SS is high. If this function is not used, leave

this pin floating.

ADJ (Pin K7): The LTM8025 regulates its ADJ pin to 0.79V.

Connect the adjust resistor from this pin to ground. The