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SPT7921 数据表(PDF) 4 Page - Cadeka Microcircuits LLC.

部件名 SPT7921
功能描述  12-BIT, 20 MSPS, TTL, A/D CONVERTER
PDF  11 Pages
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制造商  CADEKA [Cadeka Microcircuits LLC.]
网页  http://www.cadeka.com
标志 CADEKA - Cadeka Microcircuits LLC.

SPT7921 数据表(HTML) 4 Page - Cadeka Microcircuits LLC.

  SPT7921 Datasheet HTML 1Page - Cadeka Microcircuits LLC. SPT7921 Datasheet HTML 2Page - Cadeka Microcircuits LLC. SPT7921 Datasheet HTML 3Page - Cadeka Microcircuits LLC. SPT7921 Datasheet HTML 4Page - Cadeka Microcircuits LLC. SPT7921 Datasheet HTML 5Page - Cadeka Microcircuits LLC. SPT7921 Datasheet HTML 6Page - Cadeka Microcircuits LLC. SPT7921 Datasheet HTML 7Page - Cadeka Microcircuits LLC. SPT7921 Datasheet HTML 8Page - Cadeka Microcircuits LLC. SPT7921 Datasheet HTML 9Page - Cadeka Microcircuits LLC. Next Button
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3/10/97
SPT7921
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at TA = +25 °C. Parameter is
guaranteed over specified temperature range.
TEST LEVEL
I
II
III
IV
V
VI
PARAMETERS
DESCRIPTION
MIN
TYP
MAX
UNITS
td
CLK to Data Valid Prop Delay
-
14
18
ns
tpwH
CLK High Pulse Width
20
-
300
ns
tpwL
CLK Low Pulse Width
20
-
-
ns
Figure 1A: Timing Diagram
Table I - Timing Parameters
Figure 1B: Single Event Clock
CLK
OUTPUT
DATA
td
tt
pwH
pwL
DATA VALID
N+1
N
N+1
N+2
DATA VALID
N
N-2
N-1
DATA VALID
CLK
OUTPUT
DATA
td



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