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SPT7937 数据表(PDF) 2 Page - Cadeka Microcircuits LLC. |
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SPT7937 数据表(HTML) 2 Page - Cadeka Microcircuits LLC. |
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2 / 11 page ![]() 2 3/5/02 SPT7937 ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages AVDD ...................................................................... +6 V DVDD ..................................................................... +6 V OVDD ..................................................................... +6 V Input Voltages Analog Input ................................. –0.7 V to VDD +0.7 V CLK Input ............................................................... VDD AVDD – DVDD .................................................. ±100 mV AGND – DGND .............................................. ±100 mV Output Digital Outputs .................................................... 10 mA Temperature Operating Temperature ........................... –40 to +85 °C Junction Temperature ...................................... +175 °C Lead Temperature, (soldering 10 seconds) ...... +300 °C Storage Temperature ............................ –65 to +150 °C Note 1: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, VDD=+5.0 V, ƒS=28 MSPS, VIN=0 to 4 V, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified. TEST TEST SPT7937 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Resolution 12 Bits DC Accuracy Integral Linearity Error (ILE) V ±1.75 LSB Differential Linearity Error (DLE) V ±0.9 LSB No Missing Codes VI Guaranteed Analog Input Input Voltage Range VI VRLS VRHS V Input Capacitance V 5.0 pF Input Bandwidth V 250 MHz Input Impedance 35 k Ω –Full-Scale Error1 V 1.0 LSB +Full-Scale Error1 V 0.12 %FS Conversion Characteristics Maximum Conversion Rate VI 28 MHz Minimum Conversion Rate V 1 MHz Pipeline Delay (Latency) IV 14 Clock Cycles Aperture Delay Time (TAP) V 1.0 ns Aperture Jitter Time V 5.0 ps (RMS) Clock Duty Cycle V 40 60 % Over-Voltage Recovery Time2 36 ns Reference Input Resistance VI 350 500 650 Ω Voltage Range3 VRHS IV 3.0 VDD V VRLS IV 0.0 2.0 V VRHS – VRLS V 1.0 4.0 5.0 V Dynamic Performance Effective Number of Bits ƒIN = 3.58 MHz V 10.3 Bits ƒIN = 10 MHz VI 10.0 Bits 1 The full-scale range spans the reference ladder sense pins, VRHS and VRLS. Refer to the Voltage Reference section for discussion. 2 Due to internal architecture, over-voltage recovery time is less than one clock cycle (i.e., 25 ns at ƒCLK = 40 MHz). 3 For optimum performance, the full-scale voltage range (VRHS–VRLS) should be between 3 V to 5 V. |
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