4

2/20/01

SPT9689

SWITCHING TERMS (Refer to figure 1)

tion delay measured from the time the input signal

crosses the reference (± the input offset voltage) to

the 50% point of an output LOW to HIGH transition

delay measured from the time the input signal

crosses the reference (± the input offset voltage) to

the 50% point of an output HIGH to LOW transition

propagation delay measured from the 50% point of

the Latch Enable signal LOW to HIGH transition to

the 50% point of an output LOW to HIGH transition

the differential input and reference input voltages

propagation delay measured from the 50% point of

the Latch Enable signal LOW to HIGH transition to

the 50% point of an output HIGH to LOW transition

MINIMUM HOLD TIME – the minimum time after the

negative transition of the Latch Enable signal that

the input signal must remain unchanged in order to

be acquired and held at the outputs

MINIMUM LATCH ENABLE PULSE WIDTH – the

minimum time that the Latch Enable signal must be

HIGH in order to acquire an input signal change

MINIMUM SET-UP TIME – the minimum time before

the negative transition of the Latch Enable signal

that an input signal change must be present in order

to be acquired and held at the outputs

GENERAL INFORMATION

The SPT9689 is an ultrahigh-speed dual voltage com-

parator. It offers tight absolute characteristics. The device

has differential analog inputs and complementary logic

outputs compatible with ECL systems. The output stage is

adequate for driving terminated 50 ohm transmission

lines.

The SPT9689 has a complementary latch enable control

for each comparator. Both should be driven by standard

ECL logic levels.

The negative common mode voltage is –2.5 V. The posi-

tive common mode voltage is +4.0 V.

nections but have separate grounds for each comparator

to achieve high crosstalk rejection.

ECL

OUT

Q

Q

REF

1

REF

2

PRE

AMP

+

–

CLK

BUF

LATCH

GND

LE

LE

Figure 2 – Internal Function Diagram