5

3/21/97

SPT9687

VIN

VRef

Noninverting

Input

Inverting

Input

GND

.1 µF

Q Output

+

-

Q Output

= Represents line termination.

VCC

VEE

.1 µF

-2 V

RL

50

Ω

LE

LE

RL

50

Ω

ECL

Hysteresis is obtained by applying a DC bias to the LE pin.

Represents line termination.

VEE

VCC

VIN

VREF

Noninverting

Input

Inverting

Input

GND

.1 µF

Q OUTPUT

+

-

Q OUTPUT

LE

300

Ω

-5.2 V

VO

VIN

VLE

100

Ω

100

Ω

VLE

0.1 µF

300

Ω

LE

.1 µF

RL

50

Ω

-2 V

RL

50

Ω

-5.2 V

Figure 3 - Typical Interface Circuit

Figure 4 - Typical Interface With Hysteresis

Q

3

R 2

R

1

V

CC

V

IN

R

IN

V

IN

V

R2

VR1

V

EE

R 3

R 4

R 5

R 6

R 7

Q

2

Q

6

Q

8

Q

10

Q

12

V

PRE

Q

11

Q9

Q

5

Q

7

Q

1

Q

4

IN

1 pF

C

IN

1 pF

C

100

Ω

100

Ω

V

PRE

R

IN

Figure 5 - Equivalent Input Circuit

Figure 6 - AC Test Fixture

SEMI

RIGID

SEMI

RIGID

SEMI-

RIGID

SEMI-

RIGID

DUT

0.1 µF

0.1 µF

0.1 µF

0.1 µF

50

50

50

50

50

100

100

100

50

100

100

6

6

666

6

6

6

GND

15 µF

L1

L2

L2

L1

L1

L3

4

V+

V-

+

-

LE

LE

50

SAMPLING

SCOPE

V

V

OUT

OUT

+

-

15 µF

15 µF

TANT

+

+

-

-

LE

MONITOR

LE

LE

LE

MONITOR

(-5.2 V)

(-4.0 V)

V

IN

-

V

IN

+

V

IN

+

MONITOR

(+5.0 V)

6

Q

Q

50

Ω Coax

50

Ω

Rz

Vpd

(-4.0 V)

100

Ω

RL

100

Ω

RZ

Figure 8 - Test Load

4.5 mA

Q Output

Q Output

Q23

Q24

R7

240

Ω

R8

240

Ω

V1

Q21

Q22

V2

Figure 7 - Output Circuit