__________ Applications Information

Supply Bypassing

ic 0.1µF and 0.001µF capacitors in parallel, as close to

the device as possible, with the 0.001µF valued capaci-

tor the closest to the device. For additional supply

bypassing, place a 10µF tantalum or ceramic capacitor

at the point where power enters the circuit board.

Differential Traces

Output trace characteristics affect the performance of

the MAX9111/MAX9113. Use controlled impedance

traces to match trace impedance to both transmission

medium impedance and the termination resistor.

Eliminate reflections and ensure that noise couples as

common mode by running the differential traces close

together. Reduce skew by matching the electrical

length of the traces. Excessive skew can result in a

degradation of magnetic field cancellation.

Maintain the distance between the differential traces to

avoid discontinuities in differential impedance. Avoid

90° turns and minimize the number of vias to further

prevent impedance discontinuities.

Cables and Connectors

Transmission media should have a differential charac-

teristic impedance of about 100

Ω. Use cables and con-

nectors that have matched impedance to minimize

impedance discontinuities.

Avoid the use of unbalanced cables such as ribbon or

simple coaxial cable. Balanced cables such as twisted

pair offer superior signal quality and tend to generate

less EMI due to canceling effects. Balanced cables

tend to pick up noise as common mode, which is

rejected by the LVDS receiver.

Termination

The MAX9111/MAX9113 input differential voltage

depends on the driver current and termination resis-

tance. Refer to the MAX9110/MAX9112 differential dri-

ver data sheet for this information.

Minimize the distance between the termination resistor

and receiver inputs. Use a single 1% to 2% surface-

mount resistor across the receiver inputs.

Board Layout

For LVDS applications, a four-layer PCB that provides

separate power, ground, LVDS signals, and input sig-

nals is recommended. Isolate the input and LVDS sig-

nals from each other to prevent coupling. For best

results, separate the input and LVDS signal planes with

the power and ground planes.

Single/Dual LVDS Line Receivers with

Ultra-Low Pulse Skew in SOT23

8

_______________________________________________________________________________________

CHARGE-CURRENT

LIMIT RESISTOR

DISCHARGE

RESISTANCE

STORAGE

CAPACITOR

Cs

100pF

1M

Ω

1500

Ω

HIGH-

VOLTAGE

DC

SOURCE

DEVICE

UNDER

TEST

90%

36.8%

TIME

CURRENT WAVEFORM

PEAK-TO-PEAK RINGING

(NOT DRAWN TO SCALE)

Ir

10%

0

0

AMPERES

Figure 3a. Human Body ESD Test Modules

Figure 3b. Human Body Current Waveform