SC652

14

PCB Layout Considerations

The layout diagram in Figure 2 illustrates a proper two

layer PCB layout for the SC652 and supporting compo-

nents. Following fundamental layout rules is critical for

achieving the performance specified in the Electrical

Characteristics table. The following guidelines are rec-

ommended when developing a PCB layout:

Place all bucket and decoupling capacitors —

C1, C2, C

IN

, and C

OUT

— as close to the device as

possible.

All charge pump current passes through pins

IN, OUT, C1+, C2+, C1-, and C2-. Therefore,

ensure that all connections to these pins make

use of wide traces so that the voltage drop on

each connection is minimized.

The GND pin should be connected to a ground

plane using multiple vias to ensure proper

thermal connection for optimal heat transfer.

Make solid ground connections between the

grounds of the C

OUT

, C

IN

, and the GND pin on the

device.

Resistor R

SET

should be connected as shown in

Figure 2, close to pins IN and ISET. The place-

ment and routing shown minimizes parasitic

capacitance at the ISET pin.

C1

C2

IN

OUT

GND

CIN

Ground Plane

COUT

GND

BL1

BL2

IN

SC652

ISET

OUT

RSET

GND

Figure 2 — Recommended PCB Layout

Figure 3 shows the pads on layer 1 that should

be connected with vias to layer 2. C

IN

, C

OUT

and

the GND pin all use vias to connect to the

ground plane. The OUT pin also uses vias and

routes on layer 2.

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Applications Information (continued)

Figure 4 shows layer 2, and has only two net

connections, GND and OUT. Note that OUT is

routed around the GND pin, and does not

interfere with the ground connections between

C

IN

, C

OUT

and the GND pin. Also, layer 2 has a

blank void in the copper beneath the ISET

trace. The blank space reduces the capacitance

coupled to the ISET pin.

Figure 3 — Layer 1

Figure 4 — Layer 2

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