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CS48540 数据表(PDF) 13 Page - Cirrus Logic

部件名 CS48540
功能描述  32-bit Audio Decoder DSP Family
PDF  26 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS48540 数据表(HTML) 13 Page - Cirrus Logic

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CS485xx Family Data Sheet
32-bit Audio Decoder DSP Family
DS734F3
Copyright 2009 Cirrus Logic, Inc.
13
CONFIDENTIAL
5.8 Switching Characteristics — Internal Clock
5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode.
Parameter
Symbol
Min
Max
Unit
Internal DCLK frequency1
CS4852x-CQZ
CS4854x-CQZ
CS4856x-CQZ
CS4854x-DQZ
CS4856x-DQZ
1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until
the next power-on reset.
Fdclk
-
Fxtal
Fxtal
Fxtal
Fxtal
Fxtal
150
150
150
150
150
MHz
Internal DCLK period1
CS4852x-CQZ
CS4854x-CQZ
CS4856x-CQZ
CS4854x-DQZ
CS4856x-DQZ
DCLKP
-
6.7
6.7
6.7
6.7
6.7
1/Fxtal
1/Fxtal
1/Fxtal
1/Fxtal
1/Fxtal
ns
Parameter
Symbol
Min
Typical
Max
Units
SCP_CLK frequency1
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin
should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is Fxtal/3.
fspisck
-25
MHz
SCP_CS# falling to SCP_CLK rising
tspicss
24
-
ns
SCP_CLK low time
tspickl
20
-
ns
SCP_CLK high time
tspickh
20
-
ns
Setup time SCP_MOSI input
tspidsu
5-
ns
Hold time SCP_MOSI input
tspidh
5-
ns
SCP_CLK low to SCP_MISO output valid
tspidov
-11
ns
SCP_CLK falling to SCP_IRQ# rising
tspiirqh
-20
ns
SCP_CS# rising to SCP_IRQ# falling
tspiirql
0ns
SCP_CLK low to SCP_CS# rising
tspicsh
24
-
ns
SCP_CS# rising to SCP_MISO output high-Z
tspicsdz
-20
ns
SCP_CLK rising to SCP_BSY# falling
tspicbsyl
-3*DCLKP+20
ns



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