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CS5366 数据表(PDF) 15 Page - Cirrus Logic |
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CS5366 数据表(HTML) 15 Page - Cirrus Logic |
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15 / 42 page ![]() DS626F4 15 CS5366 SERIAL AUDIO INTERFACE - I²S/LJ TIMING The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT. Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS. Notes: 1. Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System Clocking” on page 10. 2. CLKMODE functionality described in Section 4.6.3 "Master Mode Clock Dividers" on page 24. 3. In Slave Mode, the SCLK/LRCK ratio can be set according to preference. However, chip performance is guaranteed only when using the ratios in Section 4.7 Master and Slave Clock Frequencies on page 25. Figure 3. I²S/LJ Timing Parameter Symbol Min Typ Max Unit Sample Rates Single-Speed Mode Double-Speed Mode Quad-Speed Mode - 2 54 108 - 54 108 216 kHz Master Mode SCLK Frequency SCLK Period 1/(64*216 kHz) SCLK Duty Cycle (Note 1) (CLKMODE = 0)(Note 2) (CLKMODE = 1)(Note 2) - tPERIOD tHIGH tHIGH 64*Fs 72.3 40 28 - - 50 33 64*Fs - 60 38 Hz ns % % LRCK setup before SCLK rising LRCK hold after SCLK rising tSETUP1 tHOLD1 20 20 -- ns SDOUT setup before SCLK rising SDOUT hold after SCLK rising (VLS = 1.8 V) after SCLK rising (VLS = 3.3 V) after SCLK rising (VLS = 5 V) tSETUP2 tHOLD2 tHOLD2 tHOLD2 10 20 10 5 -- ns Slave Mode SCLK Frequency (Note 3) SCLK Period 1/(64*216 kHz) SCLK Duty Cycle - tPERIOD tHIGH - 72.3 28 64*Fs - - - - 65 Hz ns % LRCK setup before SCLK rising LRCK hold after SCLK rising tSETUP1 tHOLD1 20 20 -- ns SDOUT setup before SCLK rising (VLS = 1.8 V) before SCLK rising (VLS = 3.3 V) before SCLK rising (VLS = 5 V) SDOUT hold after SCLK rising (VLS = 1.8 V) after SCLK rising (VLS = 3.3 V) after SCLK rising (VLS = 5 V) tSETUP2 tSETUP2 tSETUP2 tHOLD2 tHOLD2 tHOLD2 4 10 10 20 10 5 -- ns LRCK SDOUT SCLK data channel channel data t HOLD2 t SET UP2 t HOLD1 t SET UP1 t PERIOD t HIGH |
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