CS5530

32

DS742F2

3. PIN DESCRIPTIONS

Clock Generator

OSC1; OSC2 – Master Clock

An inverting amplifier inside the chip is connected between these pins and can be used with a

crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible)

clock (powered relative to VD+) can be supplied into the OSC2 pin to provide the master clock

for the device.

Control Pins and Serial Data I/O

CS – Chip Select

When active low, the port will recognize SCLK. When high the SDO pin will output a high

impedance state. CS should be changed when SCLK = 0.

SDI – Serial Data Input

SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK.

SDO – Serial Data Output

SDO is the serial data output. It will output a high impedance state if CS = 1.

SCLK – Serial Clock Input

A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins

respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin

will recognize clocks only when CS is low.

A0 – Logic Output (Analog), A1 – Logic Output (Analog)

The logic states of A1-A0 mimic the A1-A0 bits in the Configuration Register. Logic

Output 0 = VA-, and Logic Output 1 = VA+.

1

2

3

4

5

6

7

813

14

15

16

17

18

19

20

VREF+

VREF-

SCLK

CS

DGND

A1

A0

VA-

VA+

C2

C1

AIN1-

AIN1+

9

10

11

12

SDO

OSC1

OSC2

SERIAL DATA INPUT

LOGIC OUTPUT (ANALOG)

POSITIVE ANALOG POWER

AMPLIFIER CAPACITOR CONNECT

AMPLIFIER CAPACITOR CONNECT

DIFFERENTIAL ANALOG INPUT

CHIP SELECT

VOLTAGE REFERENCE INPUT

VOLTAGE REFERENCE INPUT

SERIAL CLOCK INPUT

POSITIVE DIGITAL POWER

DIGITAL GROUND

SERIAL DATA OUT

MASTER CLOCK

CS5530

DIFFERENTIAL ANALOG INPUT

NC

NC

SDI

VD+

NEGATIVE ANALOG POWER

MASTER CLOCK

LOGIC OUTPUT (ANALOG)